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dc.contributor.authorRadulovic, Milan
dc.contributor.authorAsifuzzaman, Kazi
dc.contributor.authorCarpenter, Paul Matthew
dc.contributor.authorRadojkovic, Petar
dc.contributor.authorAyguadé Parra, Eduard
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.contributor.otherBarcelona Supercomputing Center
dc.identifier.citationRadulovic, M., Asifuzzaman, K., Carpenter, P., Radojkovic, P., Ayguade, E. HPC benchmarking: scaling right and looking beyond the average. A: International European Conference on Parallel and Distributed Computing. "Euro-Par 2018: Parallel Processing 24th International Conference on Parallel and Distributed Computing: Turin, Italy: August 27-31, 2018: proceedings". Berlín: Springer, 2018, p. 135-146.
dc.descriptionThe final publication is available at Springer via
dc.description.abstractDesigning a balanced HPC system requires an understanding of the dominant performance bottlenecks. There is as yet no well established methodology for a unified evaluation of HPC systems and workloads that quantifies the main performance bottlenecks. In this paper, we execute seven production HPC applications on a production HPC platform, and analyse the key performance bottlenecks: FLOPS performance and memory bandwidth congestion, and the implications on scaling out. We show that the results depend significantly on the number of execution processes and granularity of measurements. We therefore advocate for guidance in the application suites, on selecting the representative scale of the experiments. Also, we propose that the FLOPS performance and memory bandwidth should be represented in terms of the proportions of time with low, moderate and severe utilization. We show that this gives much more precise and actionable evidence than the average.
dc.description.sponsorshipThis work was supported by the Spanish Ministry of Science and Technology (project TIN2015-65316-P), Generalitat de Catalunya (contracts 2014-SGR-1051 and 2014-SGR-1272), Severo Ochoa Programme (SEV-2015-0493) of the Spanish Government; and the European Union's Horizon 2020 research and innovation programme under ExaNoDe project (grant agreement No 671578).
dc.format.extent12 p.
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors::Arquitectures paral·leles
dc.subject.lcshParallel processing (Electronic computers)
dc.subject.otherHPC applications
dc.subject.otherMemory bandwidth
dc.titleHPC benchmarking: scaling right and looking beyond the average
dc.typeConference report
dc.subject.lemacProcessament en paral·lel (Ordinadors)
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.description.peerreviewedPeer Reviewed
dc.rights.accessOpen Access
dc.description.versionPostprint (author's final draft)
dc.relation.projectidinfo:eu-repo/grantAgreement/AGAUR/PRI2005-2008/2009 SGR 980
dc.relation.projectidinfo:eu-repo/grantAgreement/AGAUR/PRI2010-2013/2014 SGR 1272
dc.relation.projectidinfo:eu-repo/grantAgreement/EC/H2020/671578/EU/European Exascale Processor Memory Node Design/ExaNoDe
upcommons.citation.authorRadulovic, M.; Asifuzzaman, K.; Carpenter, P.; Radojkovic, P.; Ayguade, E.
upcommons.citation.contributorInternational European Conference on Parallel and Distributed Computing
upcommons.citation.publicationNameEuro-Par 2018: Parallel Processing 24th International Conference on Parallel and Distributed Computing: Turin, Italy: August 27-31, 2018: proceedings

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