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Replacing 6T SRAMs with 3T1D DRAMs in the L1 data cache to combat process variability
| dc.contributor.author | Liang, Xiaoyao |
| dc.contributor.author | Canal Corretger, Ramon |
| dc.contributor.author | Wei, Gu-Yeon |
| dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
| dc.date.accessioned | 2018-09-17T08:10:42Z |
| dc.date.available | 2018-09-17T08:10:42Z |
| dc.date.issued | 2008-02 |
| dc.identifier.citation | Liang, X., Canal, R., Wei, G.-Y. Replacing 6T SRAMs with 3T1D DRAMs in the L1 data cache to combat process variability. "IEEE micro", Febrer 2008, vol. 28, núm. 1, p. 60-68. |
| dc.identifier.issn | 0272-1732 |
| dc.identifier.uri | http://hdl.handle.net/2117/121204 |
| dc.description.abstract | With continued technology scaling, process variations will be especially detrimental to six-transistor static memory structures (6T SRAMs). A memory architecture using three-transistor, one-diode DRAM (3T1D) cells in the L1 data cache tolerates wide process variations with little performance degradation, making it a promising choice for on-chip cache structures for next-generation microprocessors. |
| dc.format.extent | 9 p. |
| dc.language.iso | eng |
| dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
| dc.subject.lcsh | Memory management (Computer science) |
| dc.subject.lcsh | Microprocessors |
| dc.subject.lcsh | Cache memory |
| dc.subject.other | Cache storage |
| dc.subject.other | DRAM chips |
| dc.subject.other | Microprocessor chips |
| dc.subject.other | SRAM chips |
| dc.subject.other | System-on-chip |
| dc.subject.other | Transistors |
| dc.title | Replacing 6T SRAMs with 3T1D DRAMs in the L1 data cache to combat process variability |
| dc.type | Article |
| dc.subject.lemac | Gestió de memòria (Informàtica) |
| dc.subject.lemac | Microprocessadors |
| dc.subject.lemac | Memòria cau |
| dc.contributor.group | Universitat Politècnica de Catalunya. VIRTUOS - Virtualisation and Operating Systems |
| dc.identifier.doi | 10.1109/MM.2008.12 |
| dc.description.peerreviewed | Peer Reviewed |
| dc.relation.publisherversion | https://ieeexplore.ieee.org/document/4460513/ |
| dc.rights.access | Open Access |
| local.identifier.drac | 814466 |
| dc.description.version | Postprint (published version) |
| local.citation.author | Liang, X.; Canal, R.; Wei, G.-Y. |
| local.citation.publicationName | IEEE micro |
| local.citation.volume | 28 |
| local.citation.number | 1 |
| local.citation.startingPage | 60 |
| local.citation.endingPage | 68 |
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