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dc.contributor.authorChronaki, Kallia
dc.contributor.authorCasas, Marc
dc.contributor.authorMoreto Planas, Miquel
dc.contributor.authorBosch Pons, Jaume
dc.contributor.authorBadia Sala, Rosa Maria
dc.contributor.otherBarcelona Supercomputing Center
dc.date.accessioned2018-07-27T09:01:44Z
dc.date.available2018-07-27T09:01:44Z
dc.date.issued2018-05-29
dc.identifier.citationChronaki, K. [et al.]. TaskGenX: A Hardware-Software Proposal for Accelerating Task Parallelism. A: "High Performance Computing, 33rd International Conference, ISC High Performance 2018, Frankfurt, Germany, June 24-28, 2018: proceedings". Springer, 2018, p. 389-409.
dc.identifier.isbn978-3-319-92039-9
dc.identifier.urihttp://hdl.handle.net/2117/120101
dc.description.abstractAs chip multi-processors (CMPs) are becoming more and more complex, software solutions such as parallel programming models are attracting a lot of attention. Task-based parallel programming models offer an appealing approach to utilize complex CMPs. However, the increasing number of cores on modern CMPs is pushing research towards the use of fine grained parallelism. Task-based programming models need to be able to handle such workloads and offer performance and scalability. Using specialized hardware for boosting performance of task-based programming models is a common practice in the research community. Our paper makes the observation that task creation becomes a bottleneck when we execute fine grained parallel applications with many task-based programming models. As the number of cores increases the time spent generating the tasks of the application is becoming more critical to the entire execution. To overcome this issue, we propose TaskGenX. TaskGenX offers a solution for minimizing task creation overheads and relies both on the runtime system and a dedicated hardware. On the runtime system side, TaskGenX decouples the task creation from the other runtime activities. It then transfers this part of the runtime to a specialized hardware. We draw the requirements for this hardware in order to boost execution of highly parallel applications. From our evaluation using 11 parallel workloads on both symmetric and asymmetric multicore systems, we obtain performance improvements up to 15×, averaging to 3.1× over the baseline.
dc.description.sponsorshipThis work has been supported by the RoMoL ERC Advanced Grant (GA 321253), by the European HiPEAC Network of Excellence, by the Spanish Ministry of Science and Innovation (contracts TIN2015-65316-P), by the Generalitat de Catalunya (contracts 2014-SGR-1051 and 2014-SGR-1272), and by the European Union’s Horizon 2020 research and innovation programme under grant agreement No. 671697 and No. 779877. M. Moretó has been partially supported by the Ministry of Economy and Competitiveness under Ramon y Cajal fellowship number RYC-2016-21104. Finally, the authors would like to thank Thomas Grass for his valuable help with the simulator.
dc.format.extent21 p.
dc.language.isoeng
dc.publisherSpringer
dc.subjectÀrees temàtiques de la UPC::Informàtica
dc.subject.lcshComputer software
dc.subject.lcshHigh performance computing
dc.subject.otherChip multi-processors (CMPs)
dc.subject.otherTask-based parallel programming
dc.subject.otherTaskGenX
dc.titleTaskGenX: A Hardware-Software Proposal for Accelerating Task Parallelism
dc.typeConference lecture
dc.subject.lemacSupercomputadors
dc.subject.lemacProgramació (Ordinadors)
dc.identifier.doi10.1007/978-3-319-92040-5_20
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttps://link.springer.com/chapter/10.1007/978-3-319-92040-5_20
dc.rights.accessOpen Access
local.identifier.drac28608357
dc.description.versionPostprint (author's final draft)
dc.relation.projectidinfo:eu-repo/grantAgreement/EC/FP7/321253/EU/Riding on Moore's Law/ROMOL
dc.relation.projectidinfo:eu-repo/grantAgreement/MINECO/PE2013-2016/TIN2015-65316-P
dc.relation.projectidinfo:eu-repo/grantAgreement/EC/H2020/671697/EU/Mont-Blanc 3, European scalable and power efficient HPC platform based on low-power embedded technology/Mont-Blanc 3
dc.relation.projectidinfo:eu-repo/grantAgreement/EC/H2020/779877/EU/Mont-Blanc 2020, European scalable, modular and power efficient HPC processor/Mont-Blanc 2020
dc.relation.projectidinfo:eu-repo/grantAgreement/MINECO/PE2013-2016/RYC-2016- 21104
local.citation.publicationNameHigh Performance Computing, 33rd International Conference, ISC High Performance 2018, Frankfurt, Germany, June 24-28, 2018: proceedings
local.citation.startingPage389
local.citation.endingPage409


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