Recent Submissions

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  SyRA: early system reliability analysis for cross-layer soft errors resilience in memory arrays of microprocessor systems 

  Vallero, Alessandro; Savino, Alessandro; Chatzidimitriou, Athanansios; Kaliorakis, Manolis; Kooli, Maha; Riera Villanueva, Marc; Di Natale, Giorgio; Bosio, Alberto; Canal Corretger, Ramon; Gizopoulos, Dimitris; Di Carlo, Stefano (Institute of Electrical and Electronics Engineers (IEEE), 2018-01-01)
  Article
  Open Access

  Cross-layer reliability is becoming the preferred solution when reliability is a concern in the design of a microprocessor-based system. Nevertheless, deciding how to distribute the error management across the different ...
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  Optimization of FinFET-based gain cells for low power sub-vt embedded drams 

  Amat, Esteve; Calomarde Palomino, Antonio; Canal Corretger, Ramon; Rubio Sola, Jose Antonio (2018-06-01)
  Article
  Open Access

  Sub-threshold circuits (sub-V T) are a promising alternative in the implementation of low power electronics. The implementation of gain-cell embedded DRAMs (eDRAMs) based on FinFET devices requires a careful design to ...
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  Replacing 6T SRAMs with 3T1D DRAMs in the L1 data cache to combat process variability 

  Liang, Xiaoyao; Canal Corretger, Ramon; Wei, Gu-Yeon (2008-02)
  Article
  Open Access

  With continued technology scaling, process variations will be especially detrimental to six-transistor static memory structures (6T SRAMs). A memory architecture using three-transistor, one-diode DRAM (3T1D) cells in the ...
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  Review on suitable eDRAM configurations for next nano-metric electronics era 

  Amat, Esteve; Canal Corretger, Ramon; Calomarde Palomino, Antonio; Rubio Sola, Jose Antonio (2018-03)
  Article
  Open Access

  We summarize most of our studies focused on the main reliability issues that can threat the gain-cells eDRAM behavior when it is simulated at the nano-metric device range has been collected in this review. So, to outperform ...

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