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dc.contributor.authorAmat, Esteve
dc.contributor.authorCanal Corretger, Ramon
dc.contributor.authorCalomarde Palomino, Antonio
dc.contributor.authorRubio Sola, Jose Antonio
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Enginyeria de Sistemes, Automàtica i Informàtica Industrial
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica
dc.date.accessioned2018-07-26T06:31:26Z
dc.date.available2019-04-02T00:30:44Z
dc.date.issued2018-03
dc.identifier.citationAmat, E., Canal, R., Calomarde, A., Rubio, A. Review on suitable eDRAM configurations for next nano-metric electronics era. "International journal of the Society of Materials Engineering for Resources.The Society of Materials Engineering for Resources of Japan", Març 2018, vol. 23, núm. 1, p. 22-29.
dc.identifier.issn1347-9725
dc.identifier.urihttp://hdl.handle.net/2117/119979
dc.description.abstractWe summarize most of our studies focused on the main reliability issues that can threat the gain-cells eDRAM behavior when it is simulated at the nano-metric device range has been collected in this review. So, to outperform their memory cell counterparts, we explored different technological proposals and operational regimes where it can be located. The best memory cell performance is observed for the 3T1D-eDRAM cell when it is based on FinFET devices. Both device variability and SEU appear as key reliability issues for memory cells at sub-22nm technology node.
dc.format.extent8 p.
dc.language.isoeng
dc.subjectÀrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats
dc.subject.lcshLogic circuits -- Reliability
dc.subject.othereDRAM
dc.subject.otherFinFET
dc.subject.othersub-VT
dc.subject.otherSEU
dc.titleReview on suitable eDRAM configurations for next nano-metric electronics era
dc.typeArticle
dc.subject.lemacCircuits lògics -- Fiabilitat
dc.contributor.groupUniversitat Politècnica de Catalunya. VIRTUOS - Virtualisation and Operating Systems
dc.contributor.groupUniversitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions
dc.description.peerreviewedPeer Reviewed
dc.rights.accessOpen Access
drac.iddocument23217213
dc.description.versionPostprint (author's final draft)
dc.relation.projectidinfo:eu-repo/grantAgreement/MINECO/TEC2016-75151-C3-2-R
dc.relation.projectidinfo:eu-repo/grantAgreement/MINECO/1PE/TEC2013-45638-C3-2-R
upcommons.citation.authorAmat, E., Canal, R., Calomarde, A., Rubio, A.
upcommons.citation.publishedtrue
upcommons.citation.publicationNameInternational journal of the Society of Materials Engineering for Resources.The Society of Materials Engineering for Resources of Japan
upcommons.citation.volume23
upcommons.citation.number1
upcommons.citation.startingPage22
upcommons.citation.endingPage29


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