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dc.contributor.authorRodríguez Rodríguez, Roberto
dc.contributor.authorDíaz Maag, Javier
dc.contributor.authorCastro, Fernando
dc.contributor.authorIbáñez Marín, Pablo Enrique
dc.contributor.authorChaver Martínez, Daniel A.
dc.contributor.authorViñals Yúfera, Víctor
dc.contributor.authorSáez Alcaide, Juan Carlos
dc.contributor.authorPrieto Matías, Manuel
dc.contributor.authorPiñuel, Luis
dc.contributor.authorMonreal Arnal, Teresa
dc.contributor.authorLlaberia Griñó, José M.
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2018-07-10T10:42:30Z
dc.date.available2018-10-27T00:30:29Z
dc.date.issued2018-06-01
dc.identifier.citationRodríguez, R., Díaz, J., Castro, F., Ibáñez , P., Chaver, D., Viñals, V., Sáez, J., Prieto, M., Piñuel, L., Monreal, T., Llaberia, J. Reuse Detector: improving the management of STT-RAM SLLCs. "Computer journal", 1 Juny 2018, vol. 61, núm. 6, p. 856-880.
dc.identifier.issn1460-2067
dc.identifier.urihttp://hdl.handle.net/2117/119198
dc.description.abstractVarious constraints of Static Random Access Memory (SRAM) are leading to consider new memory technologies as candidates for building on-chip shared last-level caches (SLLCs). Spin-Transfer Torque RAM (STT-RAM) is currently postulated as the prime contender due to its better energy efficiency, smaller die footprint and higher scalability. However, STT-RAM also exhibits some drawbacks, like slow and energy-hungry write operations that need to be mitigated before it can be used in SLLCs for the next generation of computers. In this work, we address these shortcomings by leveraging a new management mechanism for STT-RAM SLLCs. This approach is based on the previous observation that although the stream of references arriving at the SLLC of a Chip MultiProcessor (CMP) exhibits limited temporal locality, it does exhibit reuse locality, i.e. those blocks referenced several times manifest high probability of forthcoming reuse. As such, conventional STT-RAM SLLC management mechanisms, mainly focused on exploiting temporal locality, result in low efficient behavior. In this paper, we employ a cache management mechanism that selects the contents of the SLLC aimed to exploit reuse locality instead of temporal locality. Specifically, our proposal consists in the inclusion of a Reuse Detector (RD) between private cache levels and the STT-RAM SLLC. Its mission is to detect blocks that do not exhibit reuse, in order to avoid their insertion in the SLLC, hence reducing the number of write operations and the energy consumption in the STT-RAM. Our evaluation, using multiprogrammed workloads in quad-core, eight-core and 16-core systems, reveals that our scheme reports on average, energy reductions in the SLLC in the range of 37–30%, additional energy savings in the main memory in the range of 6–8% and performance improvements of 3% (quad-core), 7% (eight-core) and 14% (16-core) compared with an STT-RAM SLLC baseline where no RD is employed. More importantly, our approach outperforms DASCA, the state-of-the-art STT-RAM SLLC management, reporting—depending on the specific scenario and the kind of applications used—SLLC energy savings in the range of 4–11% higher than those of DASCA, delivering higher performance in the range of 1.5–14% and additional improvements in DRAM energy consumption in the range of 2–9% higher than DASCA.
dc.format.extent25 p.
dc.language.isoeng
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshMultiprocessors -- Design and construction
dc.subject.lcshCache memory
dc.subject.otherSTT-RAM
dc.subject.otherReuse detector
dc.subject.otherReuse locality
dc.subject.otherWrite filtering
dc.subject.otherEnergy savings
dc.subject.otherPerformance
dc.titleReuse Detector: improving the management of STT-RAM SLLCs
dc.typeArticle
dc.subject.lemacMultiprocessadors -- Disseny i construcció
dc.subject.lemacMemòria ràpida de treball (Informàtica)
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.identifier.doi10.1093/comjnl/bxx099
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttps://academic.oup.com/comjnl/advance-article-abstract/doi/10.1093/comjnl/bxx099/4568418
dc.rights.accessOpen Access
drac.iddocument21859165
dc.description.versionPostprint (author's final draft)
dc.relation.projectidinfo:eu-repo/grantAgreement/MINECO/TIN2015-65316-P
dc.relation.projectidinfo:eu-repo/grantAgreement/EC/H202-0687698-HIPEAC 4
upcommons.citation.authorRodríguez, R.; Díaz, J.; Castro, F.; Ibáñez, P.; Chaver, D.; Viñals, V.; Sáez, J.; Prieto, M.; Piñuel, L.; Monreal, T.; Llaberia, J.
upcommons.citation.publishedtrue
upcommons.citation.publicationNameComputer journal
upcommons.citation.volume61
upcommons.citation.number6
upcommons.citation.startingPage856
upcommons.citation.endingPage880


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