A template system for the efficient compilation of domain abstractions onto reconfigurable computers

Abstract

Past research has addressed the issue of using FPGAs as accelerators for HPC systems. However, writing low level code for an efficient, portable and scalable architecture altogether has been always a challenge. Therefore, to help-out developers of reconfigurable accelerators in dealing with these three key issues, we propose to increase the level of abstractions. Our approach is to implement domain specific abstractions for FPGA based accelerator architectures using techniques from generic programming. In this paper we explain the basic idea of a system that helps to design accelerators by template expansions (DATE). We also present evaluations of three applications for the proposed system.