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dc.contributorJiménez González, Daniel
dc.contributorMartorell Bofill, Xavier
dc.contributor.authorVidal-Piñol, Miquel
dc.date.accessioned2018-05-27T12:51:39Z
dc.date.available2018-05-27T12:51:39Z
dc.date.issued2017-10-24
dc.identifier.urihttp://hdl.handle.net/2117/117562
dc.description.abstractHPC machines are introducing more and more heterogeneity in their architecture on the road to exascale systems. The increasing complexity of the machines due to the variety of hardware architectures and accelerators makes efficient programming a task harder than ever. Heterogeneous parallel programming models, such as OmpSs@FPGA, help the programmer handle the most unfriendly parts of working with accelerators. This master thesis analyzes the OmpSs@FPGA communication system and proposes a set of techniques to overcome the problems related to it and potentially improve the performance of the applications. The results show that the techniques proposed speed up the applications under certain conditions and, most importantly, solves some of the limitations that had the previous communication system. In particular, the new techniques specially improve the explotation of fine-grain parallelism and open the door to explore new possibilities with regard to data communication and re-use. Moreover, a tool (autoVivado) that automatically manages the process of bitstream generation, from the synthesis of the HLS code to the generation of the device-tree, has been developed as part of this master thesis. autoVivado has been fully integrated with the OmpSs@FPGA compiler infrastructure, providing the programmers a way to transparently generate parallel heterogenous programs and bitstreams from OmpSs applications that use FPGA accelerators.
dc.language.isoeng
dc.publisherUniversitat Politécnica de Catalunya
dc.subjectÀrees temàtiques de la UPC::Informàtica
dc.subject.lcshSoftware engineering
dc.subject.lcshComputer architecture
dc.subject.otherArquitectura de computadors
dc.subject.otherField programmable gate array (FPGA)
dc.subject.otherComputer architecture
dc.subject.otherField programmable gate array (FPGA)
dc.subject.otherModels de programació paral·lela
dc.subject.otherComputació heterogènia
dc.subject.otherGeneració de hardware automàtica
dc.subject.otherSincronització harwdare/software
dc.subject.otherParallel programming models
dc.subject.otherHeterogeneous computing
dc.subject.otherAutomatic hardware generation
dc.subject.otherHardware/software synchronization
dc.titleSynchronization / communication techniques for OmpSs@FPGA
dc.typeMaster thesis
dc.subject.lemacEnginyeria de programari
dc.subject.lemacArquitectura d'ordinadors
dc.identifier.slug126941
dc.rights.accessOpen Access
dc.date.updated2017-11-02T05:00:25Z
dc.audience.educationlevelMàster
dc.contributor.covenanteeBarcelona Supercomputing Center


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