Analysis of clock tree implementation on ASIC block QoR
Document typeMaster thesis
Rights accessOpen Access
The scope of this project is to develop a base methodology for clock tree synthesis that can improve the base results regarding the clock structure. The analysis of results will be done with a Quality of Results sets of metrics and by analysing the physical structure of the clock. The analysis has been performed on three blocks with different physical characteristics to achieve a transversal solution. The initial tests performed have been focused on configuration options of the EDA tool used but were disregarded. The main tests upon this thesis is based are referred to the clock physical structure such as fanout constraints, slew constraints and clock cell selection. One of the main results obtained is the importance of the layout of the block to set up the optimal constraints, limiting the transversal solution approach. It is as well an important point considering the internal algorithms followed by the tool.