Multi-dimensional LUT-based digital predistorter for concurrent dual-band envelope tracking power amplifier linearization
Document typeConference lecture
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Rights accessOpen Access
This paper presents a multi lookup table (LUT) implementation scheme for the 3D distributed memory polynomial (3D-DMP) behavioral model used in Digital Predistortion (DPD) linearization for concurrent dual-band envelope tracking (ET) power amplifiers (PAs). The proposed 3DDistributed Memory LUTs (3D-DML) architecture is suitable for efficient FPGA implementation. In order to optimize the linearization performance as well as to reduce the number of resources of the 3D-DML model, a new variant of the Orthogonal Matching Pursuit (OMP) algorithm is proposed to properly select the best LUTs. Experimental results show that the proposed strategy reduces the number of LUTs (i.e. the number of coefficients) while meeting the targeted linearity levels.
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CitationPham, T., López, D., Wang, T., Montoro, G., Gilabert, P. L. Multi-dimensional LUT-based digital predistorter for concurrent dual-band envelope tracking power amplifier linearization. A: IEEE Radio & Wireless Symposium. "Proceedings of the 2018 IEEE Radio and Wireless Symposium". Institute of Electrical and Electronics Engineers (IEEE), 2018, p. 1-4.
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