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dc.contributor.authorCastillo, Emilio
dc.contributor.authorÁlvarez Martí, Lluc
dc.contributor.authorMoreto Planas, Miquel
dc.contributor.authorCasas, Marc
dc.contributor.authorVallejo, Enrique
dc.contributor.authorBosque, Jose L.
dc.contributor.authorBeivide Palacio, Ramon
dc.contributor.authorValero Cortés, Mateo
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.contributor.otherBarcelona Supercomputing Center
dc.identifier.citationCastillo, E., Álvarez, L., Moreto, M., Casas, M., Vallejo, E., Bosque, J., Beivide, R., Valero, M. Architectural support for task dependence management with flexible software scheduling. A: International Symposium on High-Performance Computer Architecture. "24th IEEE International Symposium on High Performance Computer Architecture: 24-28 February 2018, Vienna, Austria: proceedings". Institute of Electrical and Electronics Engineers (IEEE), 2018, p. 283-295.
dc.description.abstractThe growing complexity of multi-core architectures has motivated a wide range of software mechanisms to improve the orchestration of parallel executions. Task parallelism has become a very attractive approach thanks to its programmability, portability and potential for optimizations. However, with the expected increase in core counts, finer-grained tasking will be required to exploit the available parallelism, which will increase the overheads introduced by the runtime system. This work presents Task Dependence Manager (TDM), a hardware/software co-designed mechanism to mitigate runtime system overheads. TDM introduces a hardware unit, denoted Dependence Management Unit (DMU), and minimal ISA extensions that allow the runtime system to offload costly dependence tracking operations to the DMU and to still perform task scheduling in software. With lower hardware cost, TDM outperforms hardware-based solutions and enhances the flexibility, adaptability and composability of the system. Results show that TDM improves performance by 12.3% and reduces EDP by 20.4% on average with respect to a software runtime system. Compared to a runtime system fully implemented in hardware, TDM achieves an average speedup of 4.2% with 7.3x less area requirements and significant EDP reductions. In addition, five different software schedulers are evaluated with TDM, illustrating its flexibility and performance gains.
dc.description.sponsorshipThis work has been supported by the RoMoL ERC Advanced Grant (GA 321253), by the European HiPEAC Network of Excellence, by the Spanish Ministry of Science and Innovation (contracts TIN2015-65316-P, TIN2016-76635-C2-2-R and TIN2016-81840-REDT), by the Generalitat de Catalunya (contracts 2014-SGR-1051 and 2014-SGR-1272), and by the European Union’s Horizon 2020 research and innovation programme under grant agreement No 671697 and No. 671610. M. Moretó has been partially supported by the Ministry of Economy and Competitiveness under Juan de la Cierva postdoctoral fellowship number JCI-2012-15047.
dc.format.extent13 p.
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshParallel processing (Electronic computers)
dc.subject.otherTask analysis
dc.subject.otherTime division multiplexing
dc.subject.otherBenchmark testing
dc.titleArchitectural support for task dependence management with flexible software scheduling
dc.typeConference report
dc.subject.lemacProcessament en paral·lel (Ordinadors)
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.description.peerreviewedPeer Reviewed
dc.rights.accessOpen Access
dc.description.versionPostprint (author's final draft)
dc.relation.projectidinfo:eu-repo/grantAgreement/EC/FP7/321253/EU/Riding on Moore's Law/ROMOL
local.citation.authorCastillo, E.; Álvarez, L.; Moreto, M.; Casas, M.; Vallejo, E.; Bosque, J.; Beivide, R.; Valero, M.
local.citation.contributorInternational Symposium on High-Performance Computer Architecture
local.citation.publicationName24th IEEE International Symposium on High Performance Computer Architecture: 24-28 February 2018, Vienna, Austria: proceedings

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