Architectural support for task dependence management with flexible software scheduling
Cita com:
hdl:2117/116233
Document typeConference report
Defense date2018
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Rights accessOpen Access
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ProjectCOMPUTACION DE ALTAS PRESTACIONES VII (MINECO-TIN2015-65316-P)
ROMOL - Riding on Moore's Law (EC-FP7-321253)
ROMOL - Riding on Moore's Law (EC-FP7-321253)
Abstract
The growing complexity of multi-core architectures has motivated a wide range of software mechanisms to improve the orchestration of parallel executions. Task parallelism has become a very attractive approach thanks to its programmability, portability and potential for optimizations. However, with the expected increase in core counts, finer-grained tasking will be required to exploit the available parallelism, which will increase the overheads introduced by the runtime system. This work presents Task Dependence Manager (TDM), a hardware/software co-designed mechanism to mitigate runtime system overheads. TDM introduces a hardware unit, denoted Dependence Management Unit (DMU), and minimal ISA extensions that allow the runtime system to offload costly dependence tracking operations to the DMU and to still perform task scheduling in software. With lower hardware cost, TDM outperforms hardware-based solutions and enhances the flexibility, adaptability and composability of the system. Results show that TDM improves performance by 12.3% and reduces EDP by 20.4% on average with respect to a software runtime system. Compared to a runtime system fully implemented in hardware, TDM achieves an average speedup of 4.2% with 7.3x less area requirements and significant EDP reductions. In addition, five different software schedulers are evaluated with TDM, illustrating its flexibility and performance gains.
CitationCastillo, E., Álvarez, L., Moreto, M., Casas, M., Vallejo, E., Bosque, J., Beivide, R., Valero, M. Architectural support for task dependence management with flexible software scheduling. A: International Symposium on High-Performance Computer Architecture. "24th IEEE International Symposium on High Performance Computer Architecture: 24-28 February 2018, Vienna, Austria: proceedings". Institute of Electrical and Electronics Engineers (IEEE), 2018, p. 283-295.
ISBN978-1-5386-3659-6
Publisher versionieeexplore.ieee.org/abstract/document/8327016
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