Show simple item record

dc.contributor.authorAmat Bertran, Esteve
dc.contributor.authorGarcía Almudéver, Carmen
dc.contributor.authorAymerich, N.
dc.contributor.authorCanal Corretger, Ramon
dc.contributor.authorRubio Sola, Jose Antonio
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica
dc.date.accessioned2018-04-04T11:32:10Z
dc.date.available2018-04-04T11:32:10Z
dc.date.issued2014-10-01
dc.identifier.citationAmat, E., García, C., Aymerich, N., Canal, R., Rubio, A. Strategies to enhance the 3T1D-DRAM cell variability robustness beyond 22 nm. "Microelectronics journal", 1 Octubre 2014, vol. 45, núm. 10, p. 1342-1347.
dc.identifier.issn0026-2692
dc.identifier.urihttp://hdl.handle.net/2117/115934
dc.description.abstract3T1D cell has been stated as a valid alternative to be implemented on L1 memory cache to substitute 6T, highly affected by device variability as technology dimensions are reduced. In this work, we have shown that 22 nm 3T1D memory cells present significant tolerance to high levels of device parameter fluctuation. Moreover, we have observed that when variability is considered the write access transistor becomes a significant detrimental element on the 3T1D cell performance. Furthermore, resizing and temperature control have been presented as some valid strategies in order to mitigate the 3T1D cell variability.
dc.format.extent6 p.
dc.language.isoeng
dc.rightsAttribution-NonCommercial-NoDerivs 3.0 Spain
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/3.0/es/
dc.subjectÀrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats
dc.subject.lcshCache memory
dc.subject.otherVariability
dc.subject.otherDRAM
dc.subject.otherTemperature
dc.subject.otherCMOS
dc.subject.otherDESIGN
dc.subject.otherCACHE
dc.titleStrategies to enhance the 3T1D-DRAM cell variability robustness beyond 22 nm
dc.typeArticle
dc.subject.lemacMemòria ràpida de treball (Informàtica)
dc.contributor.groupUniversitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions
dc.contributor.groupUniversitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors
dc.identifier.doi10.1016/j.mejo.2013.12.001
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttp://www.sciencedirect.com/science/article/pii/S0026269213002930
dc.rights.accessOpen Access
drac.iddocument15315446
dc.description.versionPostprint (author's final draft)
dc.relation.projectidinfo:eu-repo/grantAgreement/MICINN/TEC2008-01856
dc.relation.projectidinfo:eu-repo/grantAgreement/MICINN/6PN/TIN2010-18368
upcommons.citation.authorAmat, E., García, C., Aymerich, N., Canal, R., Rubio, A.
upcommons.citation.publishedtrue
upcommons.citation.publicationNameMicroelectronics journal
upcommons.citation.volume45
upcommons.citation.number10
upcommons.citation.startingPage1342
upcommons.citation.endingPage1347


Files in this item

Thumbnail

This item appears in the following Collection(s)

Show simple item record

Except where otherwise noted, content on this work is licensed under a Creative Commons license: Attribution-NonCommercial-NoDerivs 3.0 Spain