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Second order sigma-delta control of charge trapping for MOS capacitors
dc.contributor.author | Bheesayagari, Chenna Reddy |
dc.contributor.author | Gorreta Mariné, Sergio |
dc.contributor.author | Pons Nin, Joan |
dc.contributor.author | Domínguez Pumar, Manuel |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament de Teoria del Senyal i Comunicacions |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica |
dc.date.accessioned | 2018-04-03T08:14:52Z |
dc.date.available | 2019-09-01T00:25:39Z |
dc.date.issued | 2017-09-01 |
dc.identifier.citation | Bheesayagari, C., Gorreta, S., Pons, J., Dominguez, M. Second order sigma-delta control of charge trapping for MOS capacitors. "Microelectronics reliability", 1 Setembre 2017, vol. 76-77, p. 635-639. |
dc.identifier.issn | 0026-2714 |
dc.identifier.uri | http://hdl.handle.net/2117/115875 |
dc.description.abstract | This paper presents the circuit topology of a second order sigma-delta control of charge trapping for MOS capacitors. With this new topology it is possible to avoid the presence of plateaus that can be found in first-order sigma-delta modulators. Plateaus are unwanted phenomena in which the control is locked for a certain time interval (of unknown duration). In this case the control output is constant and therefore the controlled device is in fact in open-loop configuration. It is shown that the presence of plateaus is avoided in MOS capacitors using the proposed approach. |
dc.format.extent | 5 p. |
dc.language.iso | eng |
dc.subject | Àrees temàtiques de la UPC::Enginyeria electrònica |
dc.subject | Àrees temàtiques de la UPC::Enginyeria de la telecomunicació::Processament del senyal |
dc.subject.lcsh | Dielectric devices |
dc.subject.other | Charge trapping |
dc.subject.other | MOS |
dc.subject.other | Dielectric charging |
dc.subject.other | Sigma-delta |
dc.subject.other | Sliding mode control |
dc.title | Second order sigma-delta control of charge trapping for MOS capacitors |
dc.type | Article |
dc.subject.lemac | Dispositius dielèctrics |
dc.contributor.group | Universitat Politècnica de Catalunya. MNT - Grup de Recerca en Micro i Nanotecnologies |
dc.identifier.doi | 10.1016/j.microrel.2017.06.096 |
dc.description.peerreviewed | Peer Reviewed |
dc.relation.publisherversion | http://www.sciencedirect.com/science/article/pii/S0026271417302846?via%3Dihub |
dc.rights.access | Open Access |
local.identifier.drac | 21631092 |
dc.description.version | Postprint (author's final draft) |
local.citation.author | Bheesayagari, C.; Gorreta, S.; Pons, J.; Dominguez, M. |
local.citation.publicationName | Microelectronics reliability |
local.citation.volume | 76-77 |
local.citation.startingPage | 635 |
local.citation.endingPage | 639 |
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