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Synthesis of all-digital delay lines
dc.contributor.author | Moreno Vega, Alberto |
dc.contributor.author | Cortadella, Jordi |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament de Ciències de la Computació |
dc.date.accessioned | 2018-03-19T12:51:27Z |
dc.date.available | 2018-03-19T12:51:27Z |
dc.date.issued | 2017 |
dc.identifier.citation | Moreno, A., Cortadella, J. Synthesis of all-digital delay lines. A: IEEE International Symposium on Asynchronous Circuits and Systems. "23rd International Symposium on Asynchronous Circuits and Systems". Institute of Electrical and Electronics Engineers (IEEE), 2017, p. 75-82. |
dc.identifier.isbn | 978-1-5386-2749-5 |
dc.identifier.uri | http://hdl.handle.net/2117/115402 |
dc.description | © 2017 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works |
dc.description.abstract | The synthesis of delay lines (DLs) is a core task during the generation of matched delays, ring oscillator clocks or delay monitors. The main figure of merit of a DL is the fidelity to track variability. Unfortunately, complex systems have a great diversity of timing paths that exhibit different sensitivities to static and dynamic variations. Designing DLs that capture this diversity is an ardous task. This paper proposes an algorithmic approach for the synthesis of DLs that can be integrated in a conventional design flow. The algorithm uses heuristics to perform a combinatorial search in a vast space of solutions that combine different types of gates and wire lengths. The synthesized DLs are (1) all digital, i.e., built of conventional standard cells, (2) accurate in tracking variability and (3) configurable at runtime. Experimental results with a commercial standard cell library confirm the quality of the DLs that only exhibit delay mismatches of about 1% on average over all PVT corners. |
dc.format.extent | 8 p. |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.subject | Àrees temàtiques de la UPC::Informàtica |
dc.subject.lcsh | Asynchronous circuits |
dc.subject.other | Ring Oscillators |
dc.subject.other | Delay lines |
dc.subject.other | Variability |
dc.subject.other | Asynchronous circuits |
dc.title | Synthesis of all-digital delay lines |
dc.type | Conference report |
dc.subject.lemac | Circuits asíncrons |
dc.contributor.group | Universitat Politècnica de Catalunya. ALBCOM - Algorismia, Bioinformàtica, Complexitat i Mètodes Formals |
dc.identifier.doi | 10.1109/ASYNC.2017.10 |
dc.description.peerreviewed | Peer Reviewed |
dc.relation.publisherversion | http://ieeexplore.ieee.org/document/8097388/ |
dc.rights.access | Open Access |
local.identifier.drac | 21985223 |
dc.description.version | Postprint (author's final draft) |
local.citation.author | Moreno, A.; Cortadella, J. |
local.citation.contributor | IEEE International Symposium on Asynchronous Circuits and Systems |
local.citation.publicationName | 23rd International Symposium on Asynchronous Circuits and Systems |
local.citation.startingPage | 75 |
local.citation.endingPage | 82 |