Voltage noise analysis with ring oscillator clocks
Tipus de documentText en actes de congrés
EditorInstitute of Electrical and Electronics Engineers (IEEE)
Condicions d'accésAccés obert
Voltage noise is the main source of dynamic variability in integrated circuits and a major concern for the design of Power Delivery Networks (PDNs). Ring Oscillators Clocks (ROCs) have been proposed as an alternative to mitigate the negative effects of voltage noise as technology scales down and power density increases. However, their effectiveness highly depends on the design parameters of the PDN, power consumption patterns of the system and spatial locality of the ROCs within the clock domains. This paper analyzes the impact of the PDN parameters and ROC location on the robustness to voltage noise. The capability of reacting instantaneously to unpredictable voltage droops makes ROCs an attractive solution, which allows to reduce the amount of decoupling capacitance without downgrading performance. Tolerance to voltage noise and related benefits can be increased by using multiple ROCs and reducing the size of the clock domains. The analysis shows that up to 83% of the margins for voltage noise and up to 27% of the leakage power can be reduced by using local ROCs.
CitacióMachado, L., Roca, A., Cortadella, J. Voltage noise analysis with ring oscillator clocks. A: IEEE Computer Society Annual Symposium on VLSI. "2017 IEEE Computer Society Annual Symposium on VLSI: ISVLSI 2017: 3-5 July 2017, Bochum, North Rhine-Westfalia, Germany: proceedings". Institute of Electrical and Electronics Engineers (IEEE), 2017, p. 1-6.
Versió de l'editorhttp://ieeexplore.ieee.org/document/7987486/