Show simple item record

dc.contributor.authorNtinas, Vasileios
dc.contributor.authorVourkas, Ioannis
dc.contributor.authorAbusleme, Angel
dc.contributor.authorSirakoulis, Georgios
dc.contributor.authorRubio Sola, Jose Antonio
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica
dc.date.accessioned2018-02-28T18:07:44Z
dc.date.available2018-02-28T18:07:44Z
dc.date.issued2018-02-01
dc.identifier.citationNtinas, V., Vourkas, I., Abusleme, A., Sirakoulis, G., Rubio, A. Experimental study of artificial neural networks using a digital memristor simulator. "IEEE Transactions on Neural Networks and Learning Systems", 1 Febrer 2018, vol. 29, núm. 10, p. 5098-5110.
dc.identifier.issn2162-237X
dc.identifier.urihttp://hdl.handle.net/2117/114660
dc.description© 2018 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
dc.description.abstractThis paper presents a fully digital implementation of a memristor hardware simulator, as the core of an emulator, based on a behavioral model of voltage-controlled threshold-type bipolar memristors. Compared to other analog solutions, the proposed digital design is compact, easily reconfigurable, demonstrates very good matching with the mathematical model on which it is based, and complies with all the required features for memristor emulators. We validated its functionality using Altera Quartus II and ModelSim tools targeting low-cost yet powerful field programmable gate array (FPGA) families. We tested its suitability for complex memristive circuits as well as its synapse functioning in artificial neural networks (ANNs), implementing examples of associative memory and unsupervised learning of spatio-temporal correlations in parallel input streams using a simplified STDP. We provide the full circuit schematics of all our digital circuit designs and comment on the required hardware resources and their scaling trends, thus presenting a design framework for applications based on our hardware simulator.
dc.format.extent13 p.
dc.language.isoeng
dc.subjectÀrees temàtiques de la UPC::Enginyeria electrònica::Circuits electrònics
dc.subjectÀrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats
dc.subject.lcshNeural networks (Computer science)
dc.subject.lcshIntegrated circuits
dc.subject.otherAssociative memory
dc.subject.otherComputing
dc.subject.otherEmulator
dc.subject.otherMemristor
dc.subject.otherNeural network
dc.subject.otherNeuromorphic
dc.subject.otherResistive switching
dc.titleExperimental study of artificial neural networks using a digital memristor simulator
dc.typeArticle
dc.subject.lemacXarxes neuronals (Informàtica)
dc.subject.lemacCircuits integrats
dc.contributor.groupUniversitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions
dc.identifier.doi10.1109/TNNLS.2018.2791458
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttp://ieeexplore.ieee.org/document/8278839/
dc.rights.accessOpen Access
local.identifier.drac21998978
dc.description.versionPostprint (author's final draft)
dc.relation.projectidinfo:eu-repo/grantAgreement/MINECO//TEC2013-45638-C3-2-R/ES/APROXIMACION MULTINIVEL AL DISEÑO ORIENTADO A LA FIABILIDAD DE CIRCUITOS INTEGRADOS ANALOGICOS Y DIGITALES/
dc.relation.projectidinfo:eu-repo/grantAgreement/MINECO/1PE/TEC2016-75151-C3-2-R
local.citation.authorNtinas, V.; Vourkas, I.; Abusleme, A.; Sirakoulis, G.; Rubio, A.
local.citation.publicationNameIEEE Transactions on Neural Networks and Learning Systems
local.citation.startingPage1
local.citation.endingPage13


Files in this item

Thumbnail

This item appears in the following Collection(s)

Show simple item record