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dc.contributor.authorSuárez Gracía, Dario
dc.contributor.authorMonreal Arnal, Teresa
dc.contributor.authorViñals Yúfera, Víctor
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2018-02-16T08:07:08Z
dc.date.available2018-02-16T08:07:08Z
dc.date.issued2011
dc.identifier.citationSuárez, D., Monreal, T., Viñals, V. A comparison of cache hierarchies for SMT processors. A: Jornadas de Paralelismo. "XXII Jornadas de Paralelismo: La Laguna, 7-9 septiembre 2011: actas". La Laguna, Tenerife: Universidad de La Laguna. Servicio de Publicaciones, 2011, p. 563-568.
dc.identifier.isbn978-84-694-1791-1
dc.identifier.urihttp://hdl.handle.net/2117/114160
dc.description.abstractIn the multithread and multicore era, programs are forced to share part of the processor structures. On one hand, the state of the art in multithreading describes how efficiently manage and distribute inner resources such as reorder buffer or issue windows. On the other hand, there is a substantial body of works focused on outer resources, mainly on how to effectively share last level caches in multicores. Between these ends, first and second level caches have remained apart even if they are shared in most commercial multithreaded processors. This work analyzes multiprogrammed workloads as the worst-case scenario for cache sharing among threads. In order to obtain representative results, we present a sampling-based methodology that for multiple metrics such as STP, ANTT, IPC throughput, or fairness, reduces simulation time up to 4 orders of magnitude when running 8-thread workloads with an error lower than 3% and a confidence level of 97%. With the above mentioned methodology, we compare several state-of-the-art cache hierarchies, and observe that Light NUCA provides performance benefits in SMT processors regardless the organization of the last level cache. Most importantly, Light NUCA gains are consistent across the entire number of simulated threads, from one to eight.
dc.format.extent6 p.
dc.language.isoeng
dc.publisherUniversidad de La Laguna. Servicio de Publicaciones
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors::Arquitectures paral·leles
dc.subject.lcshCache memory
dc.subject.lcshSimultaneous multithreading processors
dc.subject.lcshMicroprocessors
dc.subject.otherCache hierarcy
dc.subject.otherMultithreading
dc.subject.otherSimulation
dc.subject.otherSampling
dc.subject.otherNUCA
dc.titleA comparison of cache hierarchies for SMT processors
dc.typeConference report
dc.subject.lemacMemòria ràpida de treball (Informàtica)
dc.subject.lemacMicroprocessadors
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.description.peerreviewedPeer Reviewed
dc.rights.accessOpen Access
local.identifier.drac21870878
dc.description.versionPostprint (author's final draft)
local.citation.authorSuárez, D.; Monreal, T.; Viñals, V.
local.citation.contributorJornadas de Paralelismo
local.citation.pubplaceLa Laguna, Tenerife
local.citation.publicationNameXXII Jornadas de Paralelismo: La Laguna, 7-9 septiembre 2011: actas
local.citation.startingPage563
local.citation.endingPage568


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