HW/SW co-designed processors: Challenges, design choices and a simulation infrastructure for evaluation
Tipo de documentoTexto en actas de congreso
Fecha de publicación2017
EditorInstitute of Electrical and Electronics Engineers (IEEE)
Condiciones de accesoAcceso abierto
Improving single thread performance is a key challenge in modern microprocessors especially because the traditional approach of increasing clock frequency and deep pipelining cannot be pushed further due to power constraints. Therefore, researchers have been looking at unconventional architectures to boost single thread performance without running into the power wall. HW/SW co-designed processors like Nvidia Denver, are emerging as a promising alternative. However, HW/SW co-designed processors need to address some key challenges such as startup delay, providing high performance with simple hardware, translation/optimization overhead, etc. before they can become mainstream. A fundamental requirement for evaluating different design choices and trade-offs to meet these challenges is to have a simulation infrastructure. Unfortunately, there is no such infrastructure available today. Building the aforementioned infrastructure itself poses significant challenges as it encompasses the complexities of not only an architectural framework but also of a compilation one. This paper identifies the key challenges that HW/SW codesigned processors face and the basic requirements for a simulation infrastructure targeting these architectures. Furthermore, the paper presents DARCO, a simulation infrastructure to enable research in this domain.
CitaciónKumar, R., Cano, J., Brankovic, A., Pavlou, D., Stavrou, K., Gibert, E., Martínez, A., González, A. HW/SW co-designed processors: Challenges, design choices and a simulation infrastructure for evaluation. A: IEEE International Symposium on Performance Analysis of Systems and Software. "ISPASS 2017: IEEE International Symposium on Performance Analysis of Systems and Software: April 24-25, 2017, Santa Rosa, California". San Francisco, CA: Institute of Electrical and Electronics Engineers (IEEE), 2017, p. 185-194.