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dc.contributor.authorAmat, Esteve
dc.contributor.authorCalomarde Palomino, Antonio
dc.contributor.authorCanal Corretger, Ramon
dc.contributor.authorRubio Sola, Jose Antonio
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Enginyeria de Sistemes, Automàtica i Informàtica Industrial
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica
dc.date.accessioned2018-02-01T14:42:34Z
dc.date.issued2017
dc.identifier.citationAmat, E., Calomarde, A., Canal, R., Rubio, A. Suitability of FinFET introduction into eDRAM cells for operate at sub-threshold level. A: International Workshop on Power and Timing Modeling, Optimization and Simulation. "27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS 2017): Thessaloniki, Greece, Sept. 25-27, 2017". Thessaloniki: Institute of Electrical and Electronics Engineers (IEEE), 2017, p. 1-6.
dc.identifier.isbn9781509064618
dc.identifier.urihttp://hdl.handle.net/2117/113578
dc.description.abstractThis paper explores the feasibility, in terms of performance and reliability, of gain-cell embedded DRAM (eDRAM) to be operative at sub-threshold range, when they are implemented with 10 nm FinFET devices. The use of individual transistor resizing in order to achieve better cell performance (i.e. retention time, access time, and energy consumption) at the sub-VT operating level is studied. In this scenario, asymmetrically resizing the memory cell, since we modify the channel length of the write access transistor and the width of the rest of the devices in the eDRAM cell, entails a 3.5x increase in retention time as compared to the nominal case and with smaller area overhead. Moreover, such a resizing significantly improves reliability against variability and soft errors (50% and 1.9x, respectively) when the cells are operated at sub-VT level.
dc.format.extent6 p.
dc.language.isoeng
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.rightsAttribution-NonCommercial-NoDerivs 3.0 Spain
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/3.0/es/
dc.subjectÀrees temàtiques de la UPC::Enginyeria electrònica
dc.subject.lcshElectronics
dc.subject.otherFinFET
dc.subject.othereDRAM
dc.subject.othersub-VT
dc.subject.othersingle event upsets
dc.subject.othervariability
dc.subject.otherreliability.
dc.titleSuitability of FinFET introduction into eDRAM cells for operate at sub-threshold level
dc.typeConference lecture
dc.subject.lemacEnginyeria electrònica
dc.contributor.groupUniversitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions
dc.contributor.groupUniversitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors
dc.identifier.doi10.1109/PATMOS.2017.8106951
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttp://ieeexplore.ieee.org/document/8106951/
dc.rights.accessRestricted access - publisher's policy
drac.iddocument21640128
dc.description.versionPostprint (author's final draft)
dc.date.lift10000-01-01
upcommons.citation.authorAmat, E., Calomarde, A., Canal, R., Rubio, A.
upcommons.citation.contributorInternational Workshop on Power and Timing Modeling, Optimization and Simulation
upcommons.citation.pubplaceThessaloniki
upcommons.citation.publishedtrue
upcommons.citation.publicationName27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS 2017): Thessaloniki, Greece, Sept. 25-27, 2017
upcommons.citation.startingPage1
upcommons.citation.endingPage6


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Except where otherwise noted, content on this work is licensed under a Creative Commons license: Attribution-NonCommercial-NoDerivs 3.0 Spain