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Suitability of FinFET introduction into eDRAM cells for operate at sub-threshold level
dc.contributor.author | Amat, Esteve |
dc.contributor.author | Calomarde Palomino, Antonio |
dc.contributor.author | Canal Corretger, Ramon |
dc.contributor.author | Rubio Sola, Jose Antonio |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Enginyeria de Sistemes, Automàtica i Informàtica Industrial |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica |
dc.date.accessioned | 2018-02-01T14:42:34Z |
dc.date.issued | 2017 |
dc.identifier.citation | Amat, E., Calomarde, A., Canal, R., Rubio, A. Suitability of FinFET introduction into eDRAM cells for operate at sub-threshold level. A: International Workshop on Power and Timing Modeling, Optimization and Simulation. "27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS 2017): Thessaloniki, Greece, Sept. 25-27, 2017". Thessaloniki: Institute of Electrical and Electronics Engineers (IEEE), 2017, p. 1-6. |
dc.identifier.isbn | 9781509064618 |
dc.identifier.uri | http://hdl.handle.net/2117/113578 |
dc.description.abstract | This paper explores the feasibility, in terms of performance and reliability, of gain-cell embedded DRAM (eDRAM) to be operative at sub-threshold range, when they are implemented with 10 nm FinFET devices. The use of individual transistor resizing in order to achieve better cell performance (i.e. retention time, access time, and energy consumption) at the sub-VT operating level is studied. In this scenario, asymmetrically resizing the memory cell, since we modify the channel length of the write access transistor and the width of the rest of the devices in the eDRAM cell, entails a 3.5x increase in retention time as compared to the nominal case and with smaller area overhead. Moreover, such a resizing significantly improves reliability against variability and soft errors (50% and 1.9x, respectively) when the cells are operated at sub-VT level. |
dc.format.extent | 6 p. |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.rights | Attribution-NonCommercial-NoDerivs 3.0 Spain |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/3.0/es/ |
dc.subject | Àrees temàtiques de la UPC::Enginyeria electrònica |
dc.subject.lcsh | Electronics |
dc.subject.other | FinFET |
dc.subject.other | eDRAM |
dc.subject.other | sub-VT |
dc.subject.other | single event upsets |
dc.subject.other | variability |
dc.subject.other | reliability. |
dc.title | Suitability of FinFET introduction into eDRAM cells for operate at sub-threshold level |
dc.type | Conference lecture |
dc.subject.lemac | Enginyeria electrònica |
dc.contributor.group | Universitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions |
dc.contributor.group | Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors |
dc.identifier.doi | 10.1109/PATMOS.2017.8106951 |
dc.description.peerreviewed | Peer Reviewed |
dc.relation.publisherversion | http://ieeexplore.ieee.org/document/8106951/ |
dc.rights.access | Restricted access - publisher's policy |
local.identifier.drac | 21640128 |
dc.description.version | Postprint (author's final draft) |
dc.date.lift | 10000-01-01 |
local.citation.author | Amat, E.; Calomarde, A.; Canal, R.; Rubio, A. |
local.citation.contributor | International Workshop on Power and Timing Modeling, Optimization and Simulation |
local.citation.pubplace | Thessaloniki |
local.citation.publicationName | 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS 2017): Thessaloniki, Greece, Sept. 25-27, 2017 |
local.citation.startingPage | 1 |
local.citation.endingPage | 6 |