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dc.contributor.authorKamal, Rajeev
dc.contributor.authorMoreno Aróstegui, Juan Manuel
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica
dc.date.accessioned2018-01-22T13:58:21Z
dc.date.issued2016
dc.identifier.citationKamal, R., Moreno, J. RTL implementation and analysis of fixed priority, round robin, and matrix arbiters for the NoC’s routers. A: International Conference on Computing, Communication and Automation. "2016 International Conference on Computing, Communication and Automation (ICCCA 2016): Greater Noida, India: 29-30 April 2016". Greater Noida: Institute of Electrical and Electronics Engineers (IEEE), 2016, p. 1451-1459.
dc.identifier.isbn978-1-5090-1667-9
dc.identifier.urihttp://hdl.handle.net/2117/113051
dc.description.abstractNetworks-on-Chip (NoC) is an emerging on-chip interconnection centric platform that influences modern high speed communication infrastructure to improve the performance of many-core System-on-Chip (SoCs) designs. The core of each NoCs router involves arbiter and multiplier pairs that need to be carefully co-optimized in order to achieve an overall efficient implementation. Low transmission latency design is one of the most important parameters of NoC design. This paper uses parametric Verilog HDL to implement the designs and compares the performance in terms of power, area, and delay of different types of arbiters using for NoCs routers. The RTL implementation is performed using parametric Verilog HDL and analysis in term of power, area and delay is performed using Xilinx ISE 14.7 and Xpower Analyzer (XPA) with Xpower Estimator (XPE). The target device uses for these implementation is Vertex 6.
dc.format.extent9 p.
dc.language.isoeng
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.subjectÀrees temàtiques de la UPC::Enginyeria de la telecomunicació::Telemàtica i xarxes d'ordinadors
dc.subjectÀrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats
dc.subject.lcshComputer networks
dc.subject.lcshIntegrated circuits
dc.subject.otherNOC
dc.subject.otherRRA
dc.subject.otherFPA
dc.subject.otherRouter
dc.titleRTL implementation and analysis of fixed priority, round robin, and matrix arbiters for the NoC’s routers
dc.typeConference lecture
dc.subject.lemacOrdinadors, Xarxes d'
dc.subject.lemacCircuits integrats
dc.contributor.groupUniversitat Politècnica de Catalunya. CETpD -Centre d'Estudis Tecnològics per a l'Atenció a la Dependència i la Vida Autònoma
dc.identifier.doi10.1109/CCAA.2016.7813949
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttp://ieeexplore.ieee.org/document/7813949/
dc.rights.accessRestricted access - publisher's policy
drac.iddocument21860100
dc.description.versionPostprint (published version)
dc.date.lift10000-01-01
upcommons.citation.authorKamal, R.; Moreno, J.
upcommons.citation.contributorInternational Conference on Computing, Communication and Automation
upcommons.citation.pubplaceGreater Noida
upcommons.citation.publishedtrue
upcommons.citation.publicationName2016 International Conference on Computing, Communication and Automation (ICCCA 2016): Greater Noida, India: 29-30 April 2016
upcommons.citation.startingPage1451
upcommons.citation.endingPage1459


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