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dc.contributor.authorGonzález García, Rubén
dc.contributor.authorCristal Kestelman, Adrián
dc.contributor.authorOrtega Fernández, Daniel
dc.contributor.authorVeidenbaum, Alex
dc.contributor.authorValero Cortés, Mateo
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.identifier.citationGonzález, R., Cristal, A., Ortega, D., Veidenbaum, A., Valero, M. A content aware integer register file organization. A: International Symposium on Computer Architecture. "31st Annual International Symposium on Computer Architecture, 2004: proceedings". Munich: Institute of Electrical and Electronics Engineers (IEEE), 2004, p. 314-324.
dc.description.abstractA register file is a critical component of a modern superscalar processor. It has a large number of entries and read/write ports in order to enable high levels of instruction parallelism. As a result, the register file's area, access time, and energy consumption increase dramatically, significantly affecting the overall superscalar processor's performance and energy consumption. This is especially true in 64-bit processors. This paper presents a new integer register file organization, which reduces energy consumption, area, and access time of the register file with a minimal effect on overall IPC. This is accomplished by exploiting a new concept, partial value locality, which is defined as occurrence of multiple live value instances identical in a subset of their bits. A possible implementation of the new register file is described and shown to obtain proposed optimized register file designs. Overall, an energy reduction of over 50%, a 18% decrease in area, and a 15% reduction in the access time are achieved in the new register file. The energy and area savings are achieved with a 1.7% reduction in IPC for integer applications and a negligible 0.3% in numerical applications, assuming the same clock frequency. A performance increase of up to 13% is possible if the clock frequency can be increases due to a reduction in the register file access time. This approach enables other, very promising optimizations, three of which are outlined in the paper.
dc.format.extent11 p.
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshMicroprocessors -- Energy consumption
dc.subject.lcshParallel processing (Electronic computers)
dc.subject.otherPower consumption
dc.subject.otherParallel architectures
dc.subject.otherInstruction sets
dc.subject.otherMicroprocessor chips
dc.subject.otherFile organisation
dc.titleA content aware integer register file organization
dc.typeConference report
dc.subject.lemacMicroprocessadors -- Consum d'energia
dc.subject.lemacProcessament en paral·lel (Ordinadors)
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.description.peerreviewedPeer Reviewed
dc.rights.accessOpen Access
dc.description.versionPostprint (published version)
upcommons.citation.authorGonzález, R.; Cristal, A.; Ortega, D.; Veidenbaum, A.; Valero, M.
upcommons.citation.contributorInternational Symposium on Computer Architecture
upcommons.citation.publicationName31st Annual International Symposium on Computer Architecture, 2004: proceedings

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