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dc.contributor.authorSalamí San Juan, Esther
dc.contributor.authorValero Cortés, Mateo
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2018-01-22T12:08:47Z
dc.date.available2018-01-22T12:08:47Z
dc.date.issued2005
dc.identifier.citationSalamí, E., Valero, M. A vector-µSIMD-VLIW architecture for multimedia applications. A: International Conference on Parallel Processing. "2005 International Conference on Parallel Processing: 14-17 June 2005, Oslo, Norway: proceedings". Oslo: Institute of Electrical and Electronics Engineers (IEEE), 2005, p. 69-77.
dc.identifier.isbn0-7695-2380-3
dc.identifier.urihttp://hdl.handle.net/2117/113044
dc.description.abstractMedia processing has motivated strong changes in the focus and design of processors. These applications are composed of heterogeneous regions of code, some of them with high levels of DLP and other ones with only modest amounts of ILP. A common approach to deal with these applications are /spl mu/SIMD-VLIWprocessors. However, the ILP regions fail to scale when we increase the width of the machine, which, on the other hand, is desired to achieve high performance in the DLP regions. In this paper, we propose and evaluate adding vector capabilities to a /spl mu/SIMD-VLIW core to speed-up the execution of the DLP regions, while, at the same time, reducing the fetch bandwidth requirements. Results show that, in the DLP regions, both 2 and 4-issue width vector-/spl mu/SIMD-VLIW architectures outperform a 8-issue width /spl mu/SIMD-VLIW in factors of up to 2.7X and 4.2X (1.6X and 2.1X in average) respectively. As a result, the DLP regions become less than 10% of the total execution time and performance is dominated by the ILP regions.
dc.format.extent9 p.
dc.language.isoeng
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshMultimedia systems
dc.subject.lcshParallel computers
dc.subject.otherVector processor systems
dc.subject.otherParallel machines
dc.subject.otherParallel architectures
dc.subject.otherMultimedia computing
dc.subject.otherInstruction sets
dc.titleA vector-µSIMD-VLIW architecture for multimedia applications
dc.typeConference report
dc.subject.lemacSistemes multimèdia
dc.subject.lemacOrdinadors paral·lels
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.identifier.doi10.1109/ICPP.2005.17
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttp://ieeexplore.ieee.org/document/1488602/
dc.rights.accessOpen Access
drac.iddocument2439669
dc.description.versionPostprint (published version)
upcommons.citation.authorSalamí, E.; Valero, M.
upcommons.citation.contributorInternational Conference on Parallel Processing
upcommons.citation.pubplaceOslo
upcommons.citation.publishedtrue
upcommons.citation.publicationName2005 International Conference on Parallel Processing: 14-17 June 2005, Oslo, Norway: proceedings
upcommons.citation.startingPage69
upcommons.citation.endingPage77


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