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Quantitative analysis of vector code
dc.contributor.author | Espasa Sans, Roger |
dc.contributor.author | Valero Cortés, Mateo |
dc.contributor.author | Padua, David |
dc.contributor.author | Jiménez Castells, Marta |
dc.contributor.author | Ayguadé Parra, Eduard |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
dc.date.accessioned | 2018-01-09T11:33:28Z |
dc.date.available | 2018-01-09T11:33:28Z |
dc.date.issued | 1995 |
dc.identifier.citation | Espasa, R., Valero, M., Padua, D., Jiménez, M., Ayguadé, E. Quantitative analysis of vector code. A: Euromicro International Conference on Parallel, Distributed, and Network-Based Processing. "Euromicro Workshop on Parallel and Distributed Processing 1995: San Remo, Italy, January 25-27, 1995". San Remo: Institute of Electrical and Electronics Engineers (IEEE), 1995, p. 452-461. |
dc.identifier.isbn | 1066-6192 |
dc.identifier.uri | http://hdl.handle.net/2117/112486 |
dc.description.abstract | In this paper we present the results of a detailed simulation study of the execution of vector programs on a single processor of a Convex C3480 machine, using a subset of the Perfect Club benchmarks. We are interested in evaluating several cost/performance tradeoffs that the machine designers made in order to assess which features of the architecture severely limit the performance attainable. We present the detailed usage of the vector functional units and a study of the kinds of resource conflicts that stall the machine. The results obtained show that the resources of the vector architecture are not efficiently used mainly due to the single bus memory architecture. Other severe limitations of the machine turn out to be the lack of chaining between vector loads and vector computations, and the lack of a second general purpose functional unit. We also present some data about the port pressure on the vector register file and we see that stalls due to port conflicts are relatively high. We also consider the slow-down introduced by spill code and find that the limited number of vector registers also limits performance. |
dc.format.extent | 10 p. |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject.lcsh | Virtual computer systems |
dc.subject.lcsh | Computer architecture |
dc.subject.other | Virtual machines |
dc.subject.other | Performance evaluation |
dc.subject.other | Vector processor systems |
dc.title | Quantitative analysis of vector code |
dc.type | Conference report |
dc.subject.lemac | Sistemes virtuals (Informàtica) |
dc.subject.lemac | Arquitectura d'ordinadors |
dc.contributor.group | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
dc.identifier.doi | 10.1109/EMPDP.1995.389176 |
dc.description.peerreviewed | Peer Reviewed |
dc.relation.publisherversion | http://ieeexplore.ieee.org/document/389176/ |
dc.rights.access | Open Access |
local.identifier.drac | 2440029 |
dc.description.version | Postprint (published version) |
local.citation.author | Espasa, R.; Valero, M.; Padua, D.; Jiménez, M.; Ayguadé, E. |
local.citation.contributor | Euromicro International Conference on Parallel, Distributed, and Network-Based Processing |
local.citation.pubplace | San Remo |
local.citation.publicationName | Euromicro Workshop on Parallel and Distributed Processing 1995: San Remo, Italy, January 25-27, 1995 |
local.citation.startingPage | 452 |
local.citation.endingPage | 461 |