Heuristics for register-constrained software pipelining
Tipus de documentText en actes de congrés
EditorInstitute of Electrical and Electronics Engineers (IEEE)
Condicions d'accésAccés obert
Software Pipelining is a loop scheduling technique that extracts parallelism from loops by overlapping the execution of several consecutive iterations. There has been a significant effort to produce throughput-optimal schedules under resource constraints, and more recently to produce throughput-optimal schedules with minimum register requirements. Unfortunately even a throughput-optimal schedule with minimum register requirements is useless if it requires more registers than those available in the target machine. This paper evaluates several techniques for producing register-constrained modulo schedules: increasing the initiation interval (II) and adding spill code. We show that, in general, increasing the II performs poorly and might not converge for some loops. The paper also presents an iterative spilling mechanism that can be applied to any software pipelining technique and proposes several heuristics in order to speed-up the scheduling process
CitacióLlosa, J., Valero, M., Ayguadé, E. Heuristics for register-constrained software pipelining. A: Annual IEEE/ACM International Symposium on Microarchitecture. "Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-29: December 2-4, 1996, Paris, France". Paris: Institute of Electrical and Electronics Engineers (IEEE), 1996, p. 250-261.
Versió de l'editorhttp://ieeexplore.ieee.org/document/566466/