Software-controlled priority characterization of POWER5 processor
Document typeConference report
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Rights accessOpen Access
Due to the limitations of instruction-level parallelism, thread-level parallelism has become a popular way to improve processor performance. One example is the IBM POWER5TM processor, a two-context simultaneous-multithreaded dual-core chip. In each SMT core, the IBM POWER5 features two levels of thread resource balancing and prioritization. The first level provides automatic in-hardware resource balancing, while the second level is a software-controlled priority mechanism that presents eight levels of thread priorities. Currently, software-controlled prioritization is only used in limited number of cases in the software platforms due to lack of performance characterization of the effects of this mechanism. In this work, we characterize the effects of the software-based prioritization on several different workloads. We show that the impact of the prioritization significantly depends on the workloads coscheduled on a core. By prioritizing the right task, it is possible to obtain more than two times of throughput improvement for synthetic workloads compared to the baseline. We also present two application case studies targeting two different performance metrics: the first case study improves overall throughput by 23.7% and the second case study reduces the total execution time by 9.3%. In addition, we show the circumstances when a background thread can be run transparently without affecting the performance of the foreground thread.
CitationBoneti, C., Cazorla, F., Gioiosa, R., Buyuktosunoglu, A., Cher, C., Valero, M. Software-controlled priority characterization of POWER5 processor. A: International Symposium on Computer Arquitecture. "ISCA 2008 Proceedings: 35th International Symposium on Computer Architecture: 21-25 June 2008, Beijing, China". Beijing: Institute of Electrical and Electronics Engineers (IEEE), 2008, p. 415-426.