Balancing HPC applications through smart allocation of resources in MT processors
Tipus de documentText en actes de congrés
EditorInstitute of Electrical and Electronics Engineers (IEEE)
Condicions d'accésAccés obert
Many studies have shown that load imbalancing causes significant performance degradation in High Performance Computing (HPC) applications. Nowadays, Multi-Threaded (MT1) processors are widely used in HPC for their good performance/energy consumption and performance/cost ratios achieved sharing internal resources, like the instruction window or the physical register. Some of these processors provide the software hardware mechanisms for controlling the allocation of processor’s internal resources. In this paper, we show, for the first time, that by appropriately using these mechanisms, we are able to control the tasks speed, reducing the imbalance in parallel applications transparently to the user and, hence, reducing the total execution time. Our results show that our proposal leads to a performance improvement up to 18% for one of the NAS benchmark. For a real HPC application (much more dynamic than the benchmark) the performance improvement is 8.1%. Our results also show that, if resource allocation is not used properly, the imbalance of applications is worsened causing performance loss.
CitacióBoneti, C., Gioiosa, R., Cazorla, F., Corbalán, J., Labarta, J., Valero, M. Balancing HPC applications through smart allocation of resources in MT processors. A: IEEE International Parallel and Distributed Processing Symposium. "IEEE International Symposium on Parallel and Distributed Processing, 2008: IPDPS 2008; 14-18 April 2008, Miami, Florida, USA". Miami, Florida: Institute of Electrical and Electronics Engineers (IEEE), 2008, p. 1-12.
Versió de l'editorhttp://ieeexplore.ieee.org/document/4536293/