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dc.contributor.authorPericàs Gleim, Miquel
dc.contributor.authorCristal Kestelman, Adrián
dc.contributor.authorCazorla, Francisco
dc.contributor.authorGonzález García, Rubén
dc.contributor.authorJiménez, Daniel A.
dc.contributor.authorValero Cortés, Mateo
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2017-12-22T12:05:21Z
dc.date.available2017-12-22T12:05:21Z
dc.date.issued2007
dc.identifier.citationPericàs, M., Cristal, A., Cazorla, F., González, R., Jiménez, D. A., Valero, M. A flexible heterogeneous multi-core architecture. A: International Conference on Parallel Architectures and Compilation Techniques. "16th International Conference on Parallel Architecture and Compilation Techniques, PACT 2007: 15-19 September 2007, Brasov, Romania". Brasov: Institute of Electrical and Electronics Engineers (IEEE), 2007, p. 13-24.
dc.identifier.isbn978-0-7695-2944-8
dc.identifier.urihttp://hdl.handle.net/2117/112388
dc.description.abstractMulti-core processors naturally exploit thread-level parallelism (TLP). However, extracting instruction-level parallelism (ILP) from individual applications or threads is still a challenge as application mixes in this environment are nonuniform. Thus, multi-core processors should be flexible enough to provide high throughput for uniform parallel applications as well as high performance for more general workloads. Heterogeneous architectures are a first step in this direction, but partitioning remains static and only roughly fits application requirements. This paper proposes the Flexible Heterogeneous Mul-tiCore processor (FMC), the first dynamic heterogeneous multi-core architecture capable of reconfiguring itself to fit application requirements without programmer intervention. The basic building block of this microarchitecture is a scalable, variable-size window microarchitecture that exploits the concept of Execution Locality to provide large-window capabilities. This allows to overcome the memory wall for applications with high memory-level parallelism (MLP). The microarchitecture contains a set of small and fast cache processors that execute high locality code and a network of small in-order memory engines that together exploit low locality code. Single-threaded applications can use the entire network of cores while multi-threaded applications can efficiently share the resources. The sizing of critical structures remains small enough to handle current power envelopes. In single-threaded mode this processor is able to outperform previous state-of-the-art high-performance processor research by 12% on SpecFP. We show how in a quad- threaded/quad-core environment the processor outperforms a statically allocated configuration in both throughput and harmonic mean, two commonly used metrics to evaluate SMTperformance, by around 2-4%. This is achieved while using a very simple sharing algorithm.
dc.format.extent12 p.
dc.language.isoeng
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshSimultaneous multithreading processors
dc.subject.lcshParallel processing (Electronic computers)
dc.subject.otherReconfigurable architectures
dc.subject.otherMultiprocessing systems
dc.subject.otherMulti-threading
dc.subject.otherParallel architectures
dc.titleA flexible heterogeneous multi-core architecture
dc.typeConference report
dc.subject.lemacProcessament en paral·lel (Ordinadors)
dc.subject.lemacMultiprocessors
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.identifier.doi10.1109/PACT.2007.4336196
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttp://ieeexplore.ieee.org/document/4336196/
dc.rights.accessOpen Access
local.identifier.drac2383405
dc.description.versionPostprint (published version)
local.citation.authorPericàs, M.; Cristal, A.; Cazorla, F.; González, R.; Jiménez, D. A.; Valero, M.
local.citation.contributorInternational Conference on Parallel Architectures and Compilation Techniques
local.citation.pubplaceBrasov
local.citation.publicationName16th International Conference on Parallel Architecture and Compilation Techniques, PACT 2007: 15-19 September 2007, Brasov, Romania
local.citation.startingPage13
local.citation.endingPage24


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