| dc.contributor.author | Pericàs Gleim, Miquel |
| dc.contributor.author | Cristal Kestelman, Adrián |
| dc.contributor.author | Cazorla, Francisco |
| dc.contributor.author | González García, Rubén |
| dc.contributor.author | Jiménez, Daniel A. |
| dc.contributor.author | Valero Cortés, Mateo |
| dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
| dc.date.accessioned | 2017-12-22T12:05:21Z |
| dc.date.available | 2017-12-22T12:05:21Z |
| dc.date.issued | 2007 |
| dc.identifier.citation | Pericàs, M., Cristal, A., Cazorla, F., González, R., Jiménez, D. A., Valero, M. A flexible heterogeneous multi-core architecture. A: International Conference on Parallel Architectures and Compilation Techniques. "16th International Conference on Parallel Architecture and Compilation Techniques, PACT 2007: 15-19 September 2007, Brasov, Romania". Brasov: Institute of Electrical and Electronics Engineers (IEEE), 2007, p. 13-24. |
| dc.identifier.isbn | 978-0-7695-2944-8 |
| dc.identifier.uri | http://hdl.handle.net/2117/112388 |
| dc.description.abstract | Multi-core processors naturally exploit thread-level parallelism (TLP). However, extracting instruction-level parallelism (ILP) from individual applications or threads is still a challenge as application mixes in this environment are nonuniform. Thus, multi-core processors should be flexible enough to provide high throughput for uniform parallel applications as well as high performance for more general workloads. Heterogeneous architectures are a first step in this direction, but partitioning remains static and only roughly fits application requirements. This paper proposes the Flexible Heterogeneous Mul-tiCore processor (FMC), the first dynamic heterogeneous multi-core architecture capable of reconfiguring itself to fit application requirements without programmer intervention. The basic building block of this microarchitecture is a scalable, variable-size window microarchitecture that exploits the concept of Execution Locality to provide large-window capabilities. This allows to overcome the memory wall for applications with high memory-level parallelism (MLP). The microarchitecture contains a set of small and fast cache processors that execute high locality code and a network of small in-order memory engines that together exploit low locality code. Single-threaded applications can use the entire network of cores while multi-threaded applications can efficiently share the resources. The sizing of critical structures remains small enough to handle current power envelopes. In single-threaded mode this processor is able to outperform previous state-of-the-art high-performance processor research by 12% on SpecFP. We show how in a quad- threaded/quad-core environment the processor outperforms a statically allocated configuration in both throughput and harmonic mean, two commonly used metrics to evaluate SMTperformance, by around 2-4%. This is achieved while using a very simple sharing algorithm. |
| dc.format.extent | 12 p. |
| dc.language.iso | eng |
| dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
| dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
| dc.subject.lcsh | Simultaneous multithreading processors |
| dc.subject.lcsh | Parallel processing (Electronic computers) |
| dc.subject.other | Reconfigurable architectures |
| dc.subject.other | Multiprocessing systems |
| dc.subject.other | Multi-threading |
| dc.subject.other | Parallel architectures |
| dc.title | A flexible heterogeneous multi-core architecture |
| dc.type | Conference report |
| dc.subject.lemac | Processament en paral·lel (Ordinadors) |
| dc.subject.lemac | Multiprocessors |
| dc.contributor.group | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
| dc.identifier.doi | 10.1109/PACT.2007.4336196 |
| dc.description.peerreviewed | Peer Reviewed |
| dc.relation.publisherversion | http://ieeexplore.ieee.org/document/4336196/ |
| dc.rights.access | Open Access |
| drac.iddocument | 2383405 |
| dc.description.version | Postprint (published version) |
| upcommons.citation.author | Pericàs, M., Cristal, A., Cazorla, F., González, R., Jiménez, D. A., Valero, M. |
| upcommons.citation.contributor | International Conference on Parallel Architectures and Compilation Techniques |
| upcommons.citation.pubplace | Brasov |
| upcommons.citation.published | true |
| upcommons.citation.publicationName | 16th International Conference on Parallel Architecture and Compilation Techniques, PACT 2007: 15-19 September 2007, Brasov, Romania |
| upcommons.citation.startingPage | 13 |
| upcommons.citation.endingPage | 24 |
