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dc.contributor.authorPericàs Gleim, Miquel
dc.contributor.authorCristal Kestelman, Adrián
dc.contributor.authorGonzález García, Rubén
dc.contributor.authorJiménez González, Daniel
dc.contributor.authorValero Cortés, Mateo
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.identifier.citationPericàs, M., Cristal, A., González, R., Jiménez, D., Valero, M. Chained in-order/out-of-order doublecore architecture. A: International Symposium on Computer Architecture and High Performance Computing. "17th International Symposium on Computer Architecture and High Performance Computing, SBAC-PAD 2005: 24-27 October 2005, Rio de Janeiro, RJ, Brazil: proceedings". Rio de Janeiro: Institute of Electrical and Electronics Engineers (IEEE), 2005, p. 209-216.
dc.description.abstractComplexity is one of the most important problems facing microarchitects. It is exacerbated by the application of optimizations, by scaling to higher issue widths and, in general, by increasing the size of microprocessor structures. This paper presents a new microarchitecture, the chained in-order/out-of-order doublecore architecture (CIO2), designed to attack the problems of complexity and energy. The CIO2 architecture reorganizes the microarchitecture using the concepts of a centralized register file and the future file. The resulting architecture decouples that program state from the execution units. The simplicity of the architecture enables the implementation of three optimizations with little effort: register file banking, writeback filtering and instruction pre-execution. These optimizations allow a reduction of up to 75% in register file energy consumption. Instruction pre-execution further allows around 40% of all integer instructions to execute in the in-order front-end, considerably reducing the activity of the power-hungry issue queues in the out-of-order back-end. Moreover, these improvements are achieved with a negligible performance loss.
dc.format.extent8 p.
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshMicroprocessors -- Energy consumption
dc.subject.lcshMicroprocessors -- Design and construction
dc.subject.otherPower consumption
dc.subject.otherMemory architecture
dc.subject.otherMicroprocessor chips
dc.subject.otherFile organisation
dc.subject.otherInstruction sets
dc.titleChained in-order/out-of-order doublecore architecture
dc.typeConference report
dc.subject.lemacMicroprocessadors -- Consum d'energia
dc.subject.lemacMicroprocessadors -- Disseny i construcció
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.description.peerreviewedPeer Reviewed
dc.rights.accessOpen Access
dc.description.versionPostprint (published version)
upcommons.citation.authorPericàs, M.; Cristal, A.; González, R.; Jiménez, D.; Valero, M.
upcommons.citation.contributorInternational Symposium on Computer Architecture and High Performance Computing
upcommons.citation.pubplaceRio de Janeiro
upcommons.citation.publicationName17th International Symposium on Computer Architecture and High Performance Computing, SBAC-PAD 2005: 24-27 October 2005, Rio de Janeiro, RJ, Brazil: proceedings

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