iQ: an efficient and flexible queue-based simulation framework
Tipus de documentText en actes de congrés
EditorInstitute of Electrical and Electronics Engineers (IEEE)
Condicions d'accésAccés obert
Conventional system simulators are readily used by computer architects to design and evaluate their processor designs. These simulators provide reasonable levels of accuracy and execution detail but suffer from long simulation latencies and increased implementation complexity. In this work we propose iQ, a queue-based modeling technique that targets design space exploration and optimization studies at the core component level. iQ emulates processor elements by abstracting the implementation details into modular components composed of queue structures, delay parameters, probabilistic driven message generation and event control. Its easy reconfigurability makes iQ a highly flexible and powerful processor simulator. We have used iQ to build an Ivy Bridge and a Core 2 Duo processor model and have validated them against real hardware running SPEC CPU2006 Int achieving average error rates of 9.55% and 8.93%.
CitacióRoca, D., Nemirovsky, D., Casas, M., Moreto, M., Valero, M., Nemirovsky, M. iQ: an efficient and flexible queue-based simulation framework. A: IEEE International Symposium on the Modeling, Analysis, and Simulation of Computer and Telecommunication Systems. "25th IEEE International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems: 20–22 September 2017, Banff, AB, Canada: proceedings". Banff, Alberta: Institute of Electrical and Electronics Engineers (IEEE), 2017, p. 143-149.
Versió de l'editorieeexplore.ieee.org/document/8107440/