Reducing fetch architecture complexity using procedure inlining
Tipus de documentText en actes de congrés
EditorInstitute of Electrical and Electronics Engineers (IEEE)
Condicions d'accésAccés obert
Fetch engine performance is seriously limited by the branch prediction table access latency. This fact has lead to the development of hardware mechanisms, like prediction overriding, aimed to tolerate this latency. However, prediction overriding requires additional support and recovery mechanisms, which increases the fetch architecture complexity. In this paper, we show that this increase in complexity can be avoided if the interaction between the fetch architecture and software code optimizations is taken into account. We use aggressive procedure inlining to generate long streams of instructions that are used by the fetch engine as the basic prediction unit. We call instruction stream to a sequence of instructions from the target of a taken branch to the next taken branch. These instruction streams are long enough to feed the execution engine with instructions during multiple cycles, while a new stream prediction is being generated, and thus hiding the prediction table access latency. Our results show that the length of instruction streams compensates the increase in the instruction cache miss rate caused by inlining. We show that, using procedure inlining, the need for a prediction overriding mechanism is avoided, reducing the fetch engine complexity.
CitacióSantana, O., Ramírez, A., Valero, M. Reducing fetch architecture complexity using procedure inlining. A: Workshop on Interaction between Compilers and Computer Architecture. "INTERACT-8 2004: Eighth Workshop on Interaction between Compilers and Computer Architectures". Madrid: Institute of Electrical and Electronics Engineers (IEEE), 2004, p. 97-106.
Versió de l'editorhttp://ieeexplore.ieee.org/document/1299514/