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dc.contributor.authorRamírez Bellido, Alejandro
dc.contributor.authorLarriba Pey, Josep
dc.contributor.authorValero Cortés, Mateo
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2017-12-15T09:13:38Z
dc.date.available2017-12-15T09:13:38Z
dc.date.issued2000
dc.identifier.citationRamírez, A., Larriba, J., Valero, M. The effect of code reordering on branch prediction. A: International Conference on Parallel Architectures and Compilation Techniques. "2000 International Conference on Parallel Architectures and Compilation Techniques: October 15-19, 2000, Philadelphia, Pennsylvania: proceedings". Philadelphia: Institute of Electrical and Electronics Engineers (IEEE), 2000, p. 189-198.
dc.identifier.isbn0-7695-0622-4
dc.identifier.urihttp://hdl.handle.net/2117/112120
dc.description.abstractBranch prediction accuracy is a very important factor for superscalar processor performance. The ability to predict the outcome of a branch allows the processor to effectively use a large instruction window, and extract a larger amount of Instruction Level Parallelism (ILP). In this paper we will examine the effect of code layout optimizations on branch prediction accuracy and final processor performance. These code reordering techniques align branches so that they tend to be not taken, achieving better instruction cache performance and increasing the fetch bandwidth. Here we focus on how these optimizations affect both static and dynamic branch prediction. Code reordering mainly increases the number of not taken branches, which benefits simple static predictors, which reach over 80% prediction accuracy with optimized codes. This branch direction change produces no effects on dynamic branch prediction: on the positive side, trades negative interference for neutral or positive interference in the prediction tables; on the negative side, it causes a worse distribution of the Branch History Register (BHR), causing many possible history values to be unused. Our results show that code reordering reduces negative Pattern History Table (PHT) interference, increasing branch prediction accuracy on small branch predictors. For example, a 0.5 KB gshare improves from 91.4% to 93.6%, and a 0.4 KB gskew predictor from 93.5% to 94.4%. For larger history lengths, the large amount of not taken branches can degrade predictor performance on dealiased schemes, like the 16 KB agree predictor which goes from 96.2% to 95.8%. But processor performance not only depends on branch prediction accuracy. Layout optimized codes have much better instruction cache performance, and wider fetch bandwidth. Our results show that when all three factors are considered together; code reordering techniques always improve processor performance. For example, performance still increases by 8% with an agree predictor; which loses prediction accuracy, and it increases by 9% with a gshare predictor, which increases prediction accuracy.
dc.format.extent10 p.
dc.language.isoeng
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshCompilers (Computer programs)
dc.subject.lcshParallel processing (Electronic computers)
dc.subject.otherPerformance evaluation
dc.subject.otherParallel architectures
dc.subject.otherProgram compilers
dc.titleThe effect of code reordering on branch prediction
dc.typeConference report
dc.subject.lemacCompiladors (Programes d'ordinador)
dc.subject.lemacProcessament en paral·lel (Ordinadors)
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.identifier.doi10.1109/PACT.2000.888343
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttp://ieeexplore.ieee.org/document/888343/
dc.rights.accessOpen Access
local.identifier.drac2402679
dc.description.versionPostprint (published version)
local.citation.authorRamírez, A.; Larriba, J.; Valero, M.
local.citation.contributorInternational Conference on Parallel Architectures and Compilation Techniques
local.citation.pubplacePhiladelphia
local.citation.publicationName2000 International Conference on Parallel Architectures and Compilation Techniques: October 15-19, 2000, Philadelphia, Pennsylvania: proceedings
local.citation.startingPage189
local.citation.endingPage198


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