Trace cache redundancy: red and blue traces
Tipus de documentText en actes de congrés
EditorInstitute of Electrical and Electronics Engineers (IEEE)
Condicions d'accésAccés obert
The objective of this paper is to improve the use of the hardware resources of the trace cache mechanism, reducing the implementation cost with no performance degradation. We achieve that by eliminating the replication of traces between the instruction cache and the trace cache. As we show, the trace cache mechanism is generating a high degree of redundancy between the traces stored in the trace cache and those built by the compiler, already present in the instruction cache. Furthermore, code reordering techniques like the software trace cache arrange the basic blocks in a program so that the fall-through path is the most common, effectively increasing this trace redundancy. We propose selective trace storage to avoid trace redundancy between the trace cache and the instruction cache. A simple modification of the fill unit allows the trace cache to store only those traces containing taken branches, which can nor be obtained in a single cycle from the instruction cache. Our results show that selective trace storage and the software trace cache used on a 32 entry trace cache (2 KB) perform as well as a 2048 entry trace cache (128 KB) without the enhancements. This shows that the cooperation between hardware and software is crucial to improve the performance and reduce the requirements of hardware mechanisms in the fetch engine.
CitacióRamírez, A., Larriba, J., Valero, M. Trace cache redundancy: red and blue traces. A: International Symposium on High-Performance Computer Architecture. "Sixth International Symposium on High-Performance Computer Architecture, HPCA-6: January 8-12, 2000, Toulouse, France: proceedings". Toulouse: Institute of Electrical and Electronics Engineers (IEEE), 2000, p. 325-333.
Versió de l'editorhttp://ieeexplore.ieee.org/document/824361/