Show simple item record

dc.contributor.authorLlosa Espuny, José Francisco
dc.contributor.authorValero Cortés, Mateo
dc.contributor.authorAyguadé Parra, Eduard
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2017-12-13T12:40:58Z
dc.date.available2017-12-13T12:40:58Z
dc.date.issued1995
dc.identifier.citationLlosa, J., Valero, M., Ayguadé, E. Non-consistent dual register files to reduce register pressure. A: International Symposium on High-Performance Computer Architecture. "First IEEE Symposium on High-Performance Computer Architecture: January 22-25, 1995 Raleigh, North Carolina". Raleigh, North Carolina: Institute of Electrical and Electronics Engineers (IEEE), 1995, p. 22-31.
dc.identifier.isbn0-8186-6445-2
dc.identifier.urihttp://hdl.handle.net/2117/111899
dc.description.abstractThe continuous grow on instruction level parallelism offered by microprocessors requires a large register file and a large number of ports to access it. This paper presents the non-consistent dual register file, an alternative implementation and management of the register file. Non-consistent dual register files support the bandwidth demands and the high register requirements, penalizing neither access time nor implementation cost. The proposal is evaluated for software pipelined loops and compared against a unified register file. Empirical results show improvements on performance and a noticeable reduction of the density of memory traffic due to a reduction of the spill code. The spill code can in general increase the minimum initiation interval and decrease loop performance. Additional improvements can be obtained when the operations are scheduled having in mind the register file organization proposed.
dc.format.extent10 p.
dc.language.isoeng
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshMicroprocessors
dc.subject.lcshParallel processing (Electronic computers)
dc.subject.otherVLIW and superscalar processors
dc.subject.otherSoftware pipelining
dc.subject.otherRegister file organization
dc.subject.otherRegister allocation
dc.subject.otherSpill code
dc.titleNon-consistent dual register files to reduce register pressure
dc.typeConference report
dc.subject.lemacMicroprocessadors
dc.subject.lemacProcessament en paral·lel (Ordinadors)
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.identifier.doi10.1109/HPCA.1995.386558
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttp://ieeexplore.ieee.org/document/386558/
dc.rights.accessOpen Access
drac.iddocument2458677
dc.description.versionPostprint (published version)
upcommons.citation.authorLlosa, J., Valero, M., Ayguadé, E.
upcommons.citation.contributorInternational Symposium on High-Performance Computer Architecture
upcommons.citation.pubplaceRaleigh, North Carolina
upcommons.citation.publishedtrue
upcommons.citation.publicationNameFirst IEEE Symposium on High-Performance Computer Architecture: January 22-25, 1995 Raleigh, North Carolina
upcommons.citation.startingPage22
upcommons.citation.endingPage31


Files in this item

Thumbnail

This item appears in the following Collection(s)

Show simple item record

All rights reserved. This work is protected by the corresponding intellectual and industrial property rights. Without prejudice to any existing legal exemptions, reproduction, distribution, public communication or transformation of this work are prohibited without permission of the copyright holder