Non-consistent dual register files to reduce register pressure
Tipus de documentText en actes de congrés
EditorInstitute of Electrical and Electronics Engineers (IEEE)
Condicions d'accésAccés obert
The continuous grow on instruction level parallelism offered by microprocessors requires a large register file and a large number of ports to access it. This paper presents the non-consistent dual register file, an alternative implementation and management of the register file. Non-consistent dual register files support the bandwidth demands and the high register requirements, penalizing neither access time nor implementation cost. The proposal is evaluated for software pipelined loops and compared against a unified register file. Empirical results show improvements on performance and a noticeable reduction of the density of memory traffic due to a reduction of the spill code. The spill code can in general increase the minimum initiation interval and decrease loop performance. Additional improvements can be obtained when the operations are scheduled having in mind the register file organization proposed.
CitacióLlosa, J., Valero, M., Ayguadé, E. Non-consistent dual register files to reduce register pressure. A: International Symposium on High-Performance Computer Architecture. "First IEEE Symposium on High-Performance Computer Architecture: January 22-25, 1995 Raleigh, North Carolina". Raleigh, North Carolina: Institute of Electrical and Electronics Engineers (IEEE), 1995, p. 22-31.
Versió de l'editorhttp://ieeexplore.ieee.org/document/386558/