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dc.contributor.authorCristal Kestelman, Adrián
dc.contributor.authorOrtega, Daniel
dc.contributor.authorLlosa Espuny, José Francisco
dc.contributor.authorValero Cortés, Mateo
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2017-12-05T13:02:11Z
dc.date.available2017-12-05T13:02:11Z
dc.date.issued2004
dc.identifier.citationCristal, A., Ortega, D., Llosa, J., Valero, M. Out-of-order commit processors. A: International Symposium on High-Performance Computer Architecture. "IEE Proceedings- Software". Madrid: Institute of Electrical and Electronics Engineers (IEEE), 2004, p. 48-59.
dc.identifier.isbn0-7695-2053-7
dc.identifier.urihttp://hdl.handle.net/2117/111581
dc.description.abstractModern out-of-order processors tolerate long latency memory operations by supporting a large number of in-flight instructions. This is particularly useful in numerical applications where branch speculation is normally not a problem and where the cache hierarchy is not capable of delivering the data soon enough. In order to support more in-flight instructions, several resources have to be up-sized, such as the reorder buffer (ROB), the general purpose instructions queues, the load/store queue and the number of physical registers in the processor. However, scaling-up the number of entries in these resources is impractical because of area, cycle time, and power consumption constraints. We propose to increase the capacity of future processors by augmenting the number of in-flight instructions. Instead of simply up-sizing resources, we push for new and novel microarchitectural structures that achieve the same performance benefits but with a much lower need for resources. Our main contribution is a new checkpointing mechanism that is capable of keeping thousands of in-flight instructions at a practically constant cost. We also propose a queuing mechanism that takes advantage of the differences in waiting time of the instructions in the flow. Using these two mechanisms our processor has a performance degradation of only 10% for SPEC2000fp over a conventional processor requiring more than an order of magnitude additional entries in the ROB and instruction queues, and about a 200% improvement over a current processor with a similar number of entries.
dc.format.extent12 p.
dc.language.isoeng
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshMicroprocessors -- Energy consumption
dc.subject.lcshParallel processing (Electronic computers)
dc.subject.lcshBuffer storage (Computer science)
dc.subject.otherSystem recovery
dc.subject.otherInstruction sets
dc.subject.otherParallel architectures
dc.subject.otherBuffer storage
dc.titleOut-of-order commit processors
dc.typeConference report
dc.subject.lemacMicroprocessadors -- Consum d'energia
dc.subject.lemacProcessament en paral·lel (Ordinadors)
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.identifier.doi10.1109/HPCA.2004.10008
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttp://ieeexplore.ieee.org/document/1410064/
dc.rights.accessOpen Access
drac.iddocument2401433
dc.description.versionPostprint (published version)
upcommons.citation.authorCristal, A., Ortega, D., Llosa, J., Valero, M.
upcommons.citation.contributorInternational Symposium on High-Performance Computer Architecture
upcommons.citation.pubplaceMadrid
upcommons.citation.publishedtrue
upcommons.citation.publicationNameIEE Proceedings- Software
upcommons.citation.startingPage48
upcommons.citation.endingPage59


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