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dc.contributor.authorRamírez, Marco Antonio
dc.contributor.authorCristal Kestelman, Adrián
dc.contributor.authorVeidenbaum, Alex
dc.contributor.authorVilla, Luis A
dc.contributor.authorValero Cortés, Mateo
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2017-12-05T12:49:33Z
dc.date.available2017-12-05T12:49:33Z
dc.date.issued2004
dc.identifier.citationRamírez, M., Cristal, A., Veidenbaum, A., Villa, L., Valero, M. Direct instruction wakeup for out-of-order processors. A: International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems. "Innovative Architecture for Future Generation High-Performance Processors and Systems: IWIA 2004: 12-14 January 2004, Maui, Hawaii: proceedings". Maui, Hawaii: Institute of Electrical and Electronics Engineers (IEEE), 2004, p. 2-9.
dc.identifier.isbn0-7695-2205-X
dc.identifier.urihttp://hdl.handle.net/2117/111579
dc.description.abstractInstruction queues consume a significant amount of power in high-performance processors, primarily due to instruction wakeup logic access to the queue structures. The wakeup logic delay is also a critical timing parameter. This paper proposes a new queue organization using a small number of successor pointers plus a small number of dynamically allocated full successor bit vectors for cases with a larger number of successors. The details of the new organization are described and it is shown to achieve the performance of CAM-based or full dependency matrix organizations using just one pointer per instruction plus eight full bit vectors. Only two full bit vectors are needed when two successor pointers are stored per instruction. Finally, a design and pre-layout of all critical structures in 70 nm technology was performed for the proposed organization as well as for a CAM-based baseline. The new design is shown to use 1/2 to 1/5th of the baseline instruction queue power, depending on queue size. It is also shown to use significantly less power than the full dependency matrix based design.
dc.format.extent8 p.
dc.language.isoeng
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshLogic design
dc.subject.lcshMicroprocessors
dc.subject.lcshParallel processing (Electronic computers)
dc.subject.otherCAM
dc.subject.otherDirect wakeup
dc.subject.otherIssue queue
dc.subject.otherLow-power
dc.subject.otherOut-of-order processors
dc.subject.otherWakeup instructions
dc.titleDirect instruction wakeup for out-of-order processors
dc.typeConference report
dc.subject.lemacEstructura lògica
dc.subject.lemacMicroprocessadors
dc.subject.lemacProcessament en paral·lel (Ordinadors)
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.identifier.doi10.1109/IWIA.2004.10002
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttp://ieeexplore.ieee.org/document/1410675/
dc.rights.accessOpen Access
drac.iddocument2401465
dc.description.versionPostprint (published version)
upcommons.citation.authorRamírez, M., Cristal, A., Veidenbaum, A., Villa, L., Valero, M.
upcommons.citation.contributorInternational Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems
upcommons.citation.pubplaceMaui, Hawaii
upcommons.citation.publishedtrue
upcommons.citation.publicationNameInnovative Architecture for Future Generation High-Performance Processors and Systems: IWIA 2004: 12-14 January 2004, Maui, Hawaii: proceedings
upcommons.citation.startingPage2
upcommons.citation.endingPage9


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