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dc.contributor.authorLiu, Qixiao
dc.contributor.authorMoreto Planas, Miquel
dc.contributor.authorAbella Ferrer, Jaume
dc.contributor.authorCazorla, Francisco
dc.contributor.authorValero Cortés, Mateo
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.contributor.otherBarcelona Supercomputing Center
dc.identifier.citationLiu, Q., Moreto, M., Abella, J., Cazorla, F., Valero, M. SEDEA: A sensible approach to account DRAM energy in multicore systems. A: International Symposium on Computer Architecture and High Performance Computing. "29th International Symposium on Computer Architecture and High Performance Computing, SBAC-PAD 2017: 17-20 October 2017, Campinas, SP, Brazil: proceedings". Campinas: Institute of Electrical and Electronics Engineers (IEEE), 2017, p. 73-80.
dc.description.abstractAs the energy cost in todays computing systems keeps increasing, measuring the energy becomes crucial in many scenarios. For instance, due to the fact that the operational cost of datacenters largely depends on the energy consumed by the applications executed, end users should be charged for the energy consumed, which requires a fair and consistent energy measuring approach. However, the use of multicore system complicates per-task energy measurement as the increased Thread Level Parallelism (TLP) allows several tasks to run simultaneously sharing resources. Therefore, the energy usage of each task is hard to determine due to interleaved activities and mutual interferences. To this end, Per-Task Energy Metering (PTEM) has been proposed to measure the actual energy of each task based on their resource utilization in a workload. However, the measured energy depends on the interferences from co-running tasks sharing the resources, and thus fails to provide the consistency across executions. Therefore, Sensible Energy Accounting (SEA) has been proposed to deliver an abstraction of the energy consumption based on a particular allocation of resources to a task.In this work we provide a realization of SEA for the DRAM memory system, SEDEA, where we account a task for the DRAM energy it would have consumed when running in isolation with a fraction of the on-chip shared cache. SEDEA is a mechanism to sensibly account for the DRAM energy of a task based on predicting its memory behavior. Our results show that SEDEA provides accurate estimates, yet with low-cost, beating existing per-task energy models, which do not target accounting energy in multicore system. We also provide a use case showing that SEDEA can be used to guide shared cache and memory bank partition schemes to save energy.
dc.description.sponsorshipThis work has been supported by the RoMoL ERC Advanced Grant (GA 321253) and National Key R&D Program of China under No.2016YFB1000204, by the European HiPEAC Network of Excellence, by the Spanish Ministry of Science and Innovation (contracts TIN2015-65316-P), by Generalitat de Catalunya (contracts 2014-SGR-1051 and 2014-SGR-1272) and by the IBM-BSC Deep Learning Center initiative. Also by the major scientific and technological project of Guangdong province (2014B010115003), and NSFC under grant no 61702495, 61672511. M. Moret´o has been partially supported by the Ministry of Economy and Competitiveness under Juan de la Cierva postdoctoral fellowship number JCI- 2012-15047. J. Abella has been partially supported by the Ministry of Economy and Competitiveness under Ramon y Cajal postdoctoral fellowship number RYC-2013-14717
dc.format.extent8 p.
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshData processing service centers -- Energy consumption
dc.subject.otherRandom access memory
dc.subject.otherMulticore processing
dc.subject.otherEnergy measurement
dc.subject.otherSea measurements
dc.titleSEDEA: A sensible approach to account DRAM energy in multicore systems
dc.typeConference report
dc.subject.lemacCentres informàtics -- Consum d'energia
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.description.peerreviewedPeer Reviewed
dc.rights.accessOpen Access
dc.description.versionPostprint (author's final draft)
dc.relation.projectidinfo:eu-repo/grantAgreement/EC/FP7/321253/EU/Riding on Moore's Law/ROMOL
local.citation.authorLiu, Q.; Moreto, M.; Abella, J.; Cazorla, F.; Valero, M.
local.citation.contributorInternational Symposium on Computer Architecture and High Performance Computing
local.citation.publicationName29th International Symposium on Computer Architecture and High Performance Computing, SBAC-PAD 2017: 17-20 October 2017, Campinas, SP, Brazil: proceedings

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