Mostra el registre d'ítem simple

dc.contributor.authorGarcía Vidal, Jorge
dc.contributor.authorMarch Hermo, María Isabel
dc.contributor.authorCerdà Alabern, Llorenç
dc.contributor.authorCorbal San Adrián, Jesús
dc.contributor.authorValero Cortés, Mateo
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2017-12-04T08:34:28Z
dc.date.available2017-12-04T08:34:28Z
dc.date.issued2004
dc.identifier.citationGarcía, J., March, M., Cerdà, L., Corbal, J., Valero, M. On the design of hybrid DRAM/SRAM memory schemes for fast packet buffers. A: International Conference on High Performance Switching and Routing. "HPSR 2004: Workshop on High Performance Switching and Routing". Phoenix, AZ: Institute of Electrical and Electronics Engineers (IEEE), 2004, p. 15-19.
dc.identifier.isbn0-7803-8375-3
dc.identifier.urihttp://hdl.handle.net/2117/111514
dc.description.abstractWe address the design of a packet buffer for future high-speed routers that support line rates as high as OC-3072 (160 Gb/s), and a high number of ports and service classes. We describe a general design for hybrid DRAM/SRAM packet buffers that exploits the bank organization of DRAM. This general scheme includes some designs previously proposed as particular cases. Based on this general scheme, we propose a new scheme that randomly chooses a DRAM memory bank for every transfer between SRAM and DRAM. The numerical results show that this scheme would require an SRAM size almost an order of magnitude lower than previously proposed schemes without the problem of memory fragmentation.
dc.format.extent5 p.
dc.language.isoeng
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshTelecommunication -- Traffic -- Management
dc.subject.lcshRouting (Computer network management)
dc.subject.otherTelecommunication network routing
dc.subject.otherDRAM chips
dc.subject.otherSRAM chips
dc.subject.otherPacket switching
dc.subject.otherBuffer storage
dc.subject.otherElectronic switching systems
dc.subject.otherQueueing theory
dc.titleOn the design of hybrid DRAM/SRAM memory schemes for fast packet buffers
dc.typeConference report
dc.subject.lemacTelecomunicació -- Tràfic -- Gestió
dc.contributor.groupUniversitat Politècnica de Catalunya. CNDS - Xarxes de Computadors i Sistemes Distribuïts
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.identifier.doi10.1109/HPSR.2004.1303414
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttp://ieeexplore.ieee.org/document/1303414/
dc.rights.accessOpen Access
drac.iddocument2325355
dc.description.versionPostprint (published version)
upcommons.citation.authorGarcía, J., March, M., Cerdà, L., Corbal, J., Valero, M.
upcommons.citation.contributorInternational Conference on High Performance Switching and Routing
upcommons.citation.pubplacePhoenix, AZ
upcommons.citation.publishedtrue
upcommons.citation.publicationNameHPSR 2004: Workshop on High Performance Switching and Routing
upcommons.citation.startingPage15
upcommons.citation.endingPage19


Fitxers d'aquest items

Thumbnail

Aquest ítem apareix a les col·leccions següents

Mostra el registre d'ítem simple

Tots els drets reservats. Aquesta obra està protegida pels drets de propietat intel·lectual i industrial corresponents. Sense perjudici de les exempcions legals existents, queda prohibida la seva reproducció, distribució, comunicació pública o transformació sense l'autorització del titular dels drets