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dc.contributor.authorCazorla Almeida, Francisco Javier
dc.contributor.authorRamírez Bellido, Alejandro
dc.contributor.authorValero Cortés, Mateo
dc.contributor.authorFernandez Prieto, Enrique
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2017-12-01T11:00:20Z
dc.date.available2017-12-01T11:00:20Z
dc.date.issued2004
dc.identifier.citationCazorla, F., Ramírez, A., Valero, M., Fernandez, E. Dynamically controlled resource allocation in SMT processors. A: Annual IEEE/ACM International Symposium on Microarchitecture. "MICRO-37 2004: 37th International Symposium on Microarchitecture, 4-8 December 2004, Portland, Oregon: proceedings". Portland, Oregon: Institute of Electrical and Electronics Engineers (IEEE), 2004, p. 171-182.
dc.identifier.isbn0-7695-2126-6
dc.identifier.urihttp://hdl.handle.net/2117/111434
dc.description.abstractSMT processors increase performance by executing instructions from several threads simultaneously. These threads use the resources of the processor better by sharing them but, at the same time, threads are competing for these resources. The way critical resources are distributed among threads determines the final performance. Currently, processor resources are distributed among threads as determined by the fetch policy that decides which threads enter the processor to compete for resources. However, current fetch policies only use indirect indicators of resource usage in their decision, which can lead to resource monopolization by a single thread or to resource waste when no thread can use them. Both situations can harm performance and happen, for example, after an L2 cache miss. In this paper, we introduce the concept of dynamic resource control in SMT processors. Using this concept, we propose a novel resource allocation policy for SMT processors. This policy directly monitors the usage of resources by each thread and guarantees that all threads get their fair share of the critical shared resources, avoiding monopolization. We also define a mechanism to allow a thread to borrow resources from another thread if that thread does not require them, thereby reducing resource under-use. Simulation results show that our dynamic resource allocation policy outperforms a static resource allocation policy by 8%, on average. It also improves the best dynamic resource-conscious fetch policies like FLUSH++ by 4%, on average, using the harmonic mean as a metric. This indicates that our policy does not obtain the ILP boost by unfairly running high ILP threads over slow memory-bounded threads. Instead, it achieves a better throughput-fairness balance.
dc.format.extent12 p.
dc.language.isoeng
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshParallel processing (Electronic computers)
dc.subject.lcshSimultaneous multithreading processors
dc.subject.otherResource management
dc.subject.otherSurface-mount technology
dc.subject.otherYarn
dc.subject.otherProcessor scheduling
dc.subject.otherComputer aided instruction
dc.subject.otherProcess control
dc.subject.otherThroughput
dc.subject.otherOperating systems
dc.subject.otherMicroarchitecture
dc.titleDynamically controlled resource allocation in SMT processors
dc.typeConference report
dc.subject.lemacMultiprocessadors
dc.subject.lemacProcessament en paral·lel (Ordinadors)
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.identifier.doi10.1109/MICRO.2004.17
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttp://ieeexplore.ieee.org/document/1550992/
dc.rights.accessOpen Access
local.identifier.drac2325375
dc.description.versionPostprint (published version)
local.citation.authorCazorla, F.; Ramírez, A.; Valero, M.; Fernandez, E.
local.citation.contributorAnnual IEEE/ACM International Symposium on Microarchitecture
local.citation.pubplacePortland, Oregon
local.citation.publicationNameMICRO-37 2004: 37th International Symposium on Microarchitecture, 4-8 December 2004, Portland, Oregon: proceedings
local.citation.startingPage171
local.citation.endingPage182


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