Performance impact of the interconnection network on MareNostrum applications
Tipus de documentText en actes de congrés
Condicions d'accésAccés obert
Interconnection networks are one of the fundamental components of a supercomputing facility, and one of the most expensive parts. They represent one of the main differences between two supercomputers built from the same processor, and have a significant impact on how the applications should be developed. However, very little is known about how those expensive interconnection networks are used by the real applications running on supercomputing facilities. Furthermore, in the near future, chip multiprocessors offering near supercomputing capabilities, with 64 to 256 processor per chip, will be readily available. Onchip interconnection networks offer the possibility of new designs with lower latencies and much higher bandwidths. In this paper we present an analysis of the impact of the interconnection network for some of the most representative applications running on MareNostrum, at the Barcelona Supercomputing Center. We have collected traces of real runs of the applications, and verified that our performance model (Dimemas) accurately predicts the real machine performance. Then, we present hypothetical situations where we change the network’s latency, bandwidth, number of simultaneous connections, and CPU speed in order to quantify their importance on the final application performance in the context of future on-chip interconnenctions. Our results show that the CPU speed proves more important than the interconnection network, and that among the network’s parameters, interconnection bandwidth is far more important than latency (with a very low impact), or the connectivity (only relevant for low connection bandwidth).
CitacióRamírez , A., Prat, O., Labarta, J., Valero, M. Performance impact of the interconnection network on MareNostrum applications. A: Workshop on Interconnection Network Architectures: On-Chip, Multi-Chip. "First Workshop on Interconnection Network Architectures: On-Chip, Multi-Chip (INA-OCMC)". Ghent: -, 2007, p. 1-6.