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dc.contributor.authorTan, Xubin
dc.contributor.authorBosch, Jaume
dc.contributor.authorVidal-Piñol, Miquel
dc.contributor.authorÁlvarez, Carlos
dc.contributor.authorJiménez-González, Daniel
dc.contributor.authorAyguadé Parra, Eduard
dc.contributor.authorValero Cortés, Mateo
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.contributor.otherBarcelona Supercomputing Center
dc.identifier.citationTan, X., Bosch, J., Vidal, M., Álvarez, C., Jiménez-González, D., Ayguade, E., Valero, M. Picos, a hardware task-dependence manager for task-based dataflow programming models. A: International Conference on High Performance Computing and Simulation. "HPCS 2017: 2017 International Conference on High Performance Computing & Simulation: proceedings: 17-21 July 2017: Genoa, Italy". Genoa: Institute of Electrical and Electronics Engineers (IEEE), 2017, p. 878-880.
dc.description.abstractTask-based programming Task-based programming models such as OpenMP, Intel TBB and OmpSs are widely used to extract high level of parallelism of applications executed on multi-core and manycore platforms. These programming models allow applications to be expressed as a set of tasks with dependences to drive their execution at runtime. While managing these dependences for task with coarse granularity proves to be highly beneficial, it introduces noticeable overheads when targeting fine-grained tasks, diminishing the potential speedups or even introducing performance losses. To overcome this drawback, we propose a hardware/software co-design Picos that manages inter-task dependences efficiently. In this paper we describe the main ideas of our proposal and a prototype implementation. This prototype is integrated with a parallel task- based programming model and evaluated with real executions in Linux embedded system with two ARM Cortex-A9 and a FPGA. When compared with a software runtime, our solution results in more than 1.8x speedup and 40% of energy savings with only 2 threads.
dc.description.sponsorshipThis work is supported by the projects SEV-2015-0493 and TIN2015-65316-P, by the project 2014-SGR-1051 and 2014-SGR-1272, by the RoMoL GA 321253 and by the project cooperation agreement with LG Electronics, and thank the Xilinx University Program.
dc.format.extent3 p.
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors::Arquitectures paral·leles
dc.subject.lcshHigh performance computing
dc.subject.lcshParallel processing (Electronic computers)
dc.subject.otherHigh performance computing
dc.subject.otherComputational modeling
dc.subject.otherField-flow fractionation
dc.subject.otherFine-grain parallelism and architectures
dc.subject.otherData flow machines
dc.subject.otherReconfigurable computing & FPGA based architectures
dc.titlePicos, a hardware task-dependence manager for task-based dataflow programming models
dc.typeConference report
dc.subject.lemacCàlcul intensiu (Informàtica)
dc.subject.lemacProcessament en paral·lel (Ordinadors)
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.rights.accessOpen Access
dc.description.versionPostprint (published version)
dc.relation.projectidinfo:eu-repo/grantAgreement/EC/FP7/321253/EU/Riding on Moore's Law/ROMOL
local.citation.authorTan, X.; Bosch, J.; Vidal, M.; Álvarez, C.; Jiménez-González, D.; Ayguade, E.; Valero, M.
local.citation.contributorInternational Conference on High Performance Computing and Simulation
local.citation.publicationNameHPCS 2017: 2017 International Conference on High Performance Computing & Simulation: proceedings: 17-21 July 2017: Genoa, Italy

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