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dc.contributor.authorEscudero, Manel
dc.contributor.authorMoll Echeto, Francisco de Borja
dc.contributor.authorRubio Sola, Jose Antonio
dc.contributor.authorVourkas, Ioannis
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica
dc.date.accessioned2017-11-20T15:01:38Z
dc.date.available2017-11-20T15:01:38Z
dc.date.issued2017
dc.identifier.citationEscudero, M., Moll, F., Rubio, A., Vourkas, I. An on-line test strategy and analysis for a 1T1R crossbar memory. A: IEEE International Symposium on On-Line Testing and Robust System Design. "2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS 2017): Thessaloniki, Greece: 3-5 July 2017". Thessaloniki: Institute of Electrical and Electronics Engineers (IEEE), 2017, p. 120-125.
dc.identifier.isbn978-1-5386-0353-6
dc.identifier.urihttp://hdl.handle.net/2117/110923
dc.description© 2017 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
dc.description.abstractMemristors are emerging devices known by their nonvolability, compatibility with CMOS processes and high density in circuits density in circuits mostly owing to the crossbar nanoarchitecture. One of their most notable applications is in the memory system field. Despite their promising characteristics and the advancements in this emerging technology, variability and reliability are still principal issues for memristors. For these reasons, exploring techniques that check the integrity of circuits is of primary importance. Therefore, this paper proposes a method to perform an on-line test capable to detect a single failure inside the memory crossbar array.
dc.format.extent6 p.
dc.language.isoeng
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.subjectÀrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors::Arquitectures paral·leles
dc.subject.lcshIntegrated circuits
dc.subject.lcshComputer architecture
dc.subject.otherMemristors
dc.subject.otherRRAM
dc.subject.otherTest
dc.titleAn on-line test strategy and analysis for a 1T1R crossbar memory
dc.typeConference report
dc.subject.lemacCircuits integrats
dc.subject.lemacArquitectura d'ordinadors
dc.contributor.groupUniversitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions
dc.identifier.doi10.1109/IOLTS.2017.8046206
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttp://ieeexplore.ieee.org/document/8046206/
dc.rights.accessOpen Access
local.identifier.drac21585497
dc.description.versionPostprint (author's final draft)
dc.relation.projectidinfo:eu-repo/grantAgreement/MINECO/1PE/TEC2016-75151-C3-2-R
dc.relation.projectidinfo:eu-repo/grantAgreement/MINECO/1PE/TEC2013-45638-C3-2-R
local.citation.authorEscudero, M.; Moll, F.; Rubio, A.; Vourkas, I.
local.citation.contributorIEEE International Symposium on On-Line Testing and Robust System Design
local.citation.pubplaceThessaloniki
local.citation.publicationName2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS 2017): Thessaloniki, Greece: 3-5 July 2017
local.citation.startingPage120
local.citation.endingPage125


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