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Reliability issues in RRAM ternary memories affected by variability and aging mechanisms

dc.contributor.authorRubio Sola, Jose Antonio
dc.contributor.authorEscudero, Manuel
dc.contributor.authorPouyan, Peyman
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica
dc.date.accessioned2017-11-20T14:50:00Z
dc.date.available2017-11-20T14:50:00Z
dc.date.issued2017
dc.identifier.citationRubio, A., Escudero, M., Pouyan, P. Reliability issues in RRAM ternary memories affected by variability and aging mechanisms. A: IEEE International Symposium on On-Line Testing and Robust System Design. "2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS 2017): Thessaloniki, Greece: 3-5 July 2017". Thessaloniki: Institute of Electrical and Electronics Engineers (IEEE), 2017, p. 90-92.
dc.identifier.isbn978-1-5386-0353-6
dc.identifier.urihttp://hdl.handle.net/2117/110921
dc.description© 2017 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
dc.description.abstractResistive switching Random Access Memories (RRAM) are being considered as a promising alternative for conventional memories mainly due to their high speed, scalability, CMOS compatibility, Non-Volatile behavior (NVM), and consequent orientation to low power consumption. Advances in the RRAM technology as well as enhancement of the control of the cells are opening the use of these devices for multi-valued logic. But the cycle-to-cycle variability and the still reduced endurance are becoming serious limitations. This paper analyzes the impact of both mechanisms on 1T1R cells and suggests potential adaptive mechanisms to enlarge its lifetime.
dc.format.extent3 p.
dc.language.isoeng
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.subjectÀrees temàtiques de la UPC::Informàtica::Sistemes d'informació::Emmagatzematge i recuperació de la informació
dc.subjectÀrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats
dc.subject.lcshComputer storage devices
dc.subject.lcshIntegrated circuits
dc.subject.otherRRAM devices
dc.subject.otherTernary memories
dc.subject.otherVariability
dc.subject.otherEndurance
dc.subject.otherAging
dc.subject.otherAdaptive mechanism
dc.titleReliability issues in RRAM ternary memories affected by variability and aging mechanisms
dc.typeConference report
dc.subject.lemacOrdinadors -- Dispositius de memòria
dc.subject.lemacCircuits integrats
dc.contributor.groupUniversitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions
dc.identifier.doi10.1109/IOLTS.2017.8046238
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttp://ieeexplore.ieee.org/document/8046238/
dc.rights.accessOpen Access
local.identifier.drac21585451
dc.description.versionPostprint (author's final draft)
dc.relation.projectidinfo:eu-repo/grantAgreement/MINECO//TEC2013-45638-C3-2-R/ES/APROXIMACION MULTINIVEL AL DISEÑO ORIENTADO A LA FIABILIDAD DE CIRCUITOS INTEGRADOS ANALOGICOS Y DIGITALES/
local.citation.authorRubio, A.; Escudero, M.; Pouyan, P.
local.citation.contributorIEEE International Symposium on On-Line Testing and Robust System Design
local.citation.pubplaceThessaloniki
local.citation.publicationName2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS 2017): Thessaloniki, Greece: 3-5 July 2017
local.citation.startingPage90
local.citation.endingPage92


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