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dc.contributor.authorNavarro Guerrero, Juan José
dc.contributor.authorCasares Giner, Vicente
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.contributor.otherFacultat d'Informàtica de Barcelona
dc.contributor.otherEscola Tècnica Superior d'Enginyeria de Telecomunicació de Barcelona
dc.date.accessioned2017-11-20T10:38:20Z
dc.date.available2017-11-20T10:38:20Z
dc.date.issued1985
dc.identifier.citationNavarro, J., Casares, V. "Systolic implementation for deconvolution iterative algorithm". 1985.
dc.identifier.urihttp://hdl.handle.net/2117/110915
dc.description.abstractSystolic architectures implement regular algorithms in hardware, in order to obtain high computational throughput. In this paper we provide a modular architecture for a deconvolution iterative algorithm. The basic module is a systolic array which implement one iteration of the algorithm recentley proposed in 1. The algorithm is a generalization of the method to invert non singular polynomial transfer function, previously publoshed in 2. The basic systoloc module can be repeteadly concatenated in such a way that can be used in real time applications.
dc.format.extent6 p.
dc.language.isoeng
dc.relation.ispartofseriesRR 85/19
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors::Arquitectures paral·leles
dc.subject.lcshSystolic array circuits
dc.subject.lcshParallel processing (Electronic computers)
dc.titleSystolic implementation for deconvolution iterative algorithm
dc.typeExternal research report
dc.subject.lemacProcessament en paral·lel (Ordinadors)
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.rights.accessOpen Access
local.identifier.drac21621855
dc.description.versionPostprint (published version)
local.citation.authorNavarro, J.; Casares, V.


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