Systolic implementation for deconvolution iterative algorithm

Abstract

Systolic architectures implement regular algorithms in hardware, in order to obtain high computational throughput. In this paper we provide a modular architecture for a deconvolution iterative algorithm. The basic module is a systolic array which implement one iteration of the algorithm recentley proposed in 1. The algorithm is a generalization of the method to invert non singular polynomial transfer function, previously publoshed in 2. The basic systoloc module can be repeteadly concatenated in such a way that can be used in real time applications.