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dc.contributorMitrani, Daniel
dc.contributorChávez Domínguez, Juan Antonio
dc.contributor.authorLópez Casablanca, Sergio
dc.date.accessioned2017-11-17T11:54:14Z
dc.date.issued2017-07
dc.identifier.urihttp://hdl.handle.net/2117/110837
dc.descriptionDiseño de controlador PID reconfigurable con FPGA
dc.language.isospa
dc.publisherUniversitat Politècnica de Catalunya
dc.subjectÀrees temàtiques de la UPC::Enginyeria de la telecomunicació
dc.subject.lcshDigital-to-analog converters
dc.subject.lcshElectronic data processing
dc.subject.otherFPGA
dc.subject.otherdata converter
dc.subject.otherVHDL
dc.subject.otherconversores
dc.subject.otherConvertidors digital/analògics
dc.titleSistema de adquisición y generación de señal basado en FPGA y placa embedded
dc.typeBachelor thesis
dc.subject.lemacConvertidors digital/analògics
dc.subject.lemacProcessament electrònic de dades
dc.identifier.slugETSETB-230.127551
dc.rights.access60 months embargo
dc.date.lift2022-11-17T11:54:14Z
dc.date.updated2017-07-19T05:51:17Z
dc.audience.educationlevelGrau
dc.audience.mediatorEscola Tècnica Superior d'Enginyeria de Telecomunicació de Barcelona


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