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dc.contributor.authorGonzález Peña, Luis Eduardo
dc.contributor.authorSanvicente Gargallo, Emilio
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Enginyeria Telemàtica
dc.contributor.otherFacultat d'Informàtica de Barcelona
dc.contributor.otherEscola Tècnica Superior d'Enginyeria de Telecomunicació de Barcelona
dc.date.accessioned2017-11-15T10:03:08Z
dc.date.available2017-11-15T10:03:08Z
dc.date.issued1985
dc.identifier.citationGonzález, L., Sanvicente, E. "An approximate analysis of synchronous multiple bus". 1985.
dc.identifier.urihttp://hdl.handle.net/2117/110658
dc.description.abstractThis paper presents an approximate analytic model for evaluating the performance of a loosely coupled multiprocessor architecture whose memory, organized in modules, is shared by all the processors. Each memory module (Mi) is associated with a particular processor (Pi), and it may be accessed by this processor (local access) or by any other processor (Pj,j<>i) through b multiple shared bussed (external access). The performance indexes used in this paper are the memory bandwith B and the delay to access a memory module. The system is evaluated for different values of p' (p'=<1), the probability of memory service requirement in each memory cycle; therefore, we allow internal processing. Also we consider two kinds of system operation, depending upon the number of cycles needed to access the requested memory when the request is for an external module. These results are obtained rather easily by solving a set of algebraic equations that approximately describe the system in steady state, and that yield performance values extremely close to the simulation results.
dc.format.extent25 p.
dc.language.isoeng
dc.relation.ispartofseriesRT 85/03
dc.subjectÀrees temàtiques de la UPC::Enginyeria de la telecomunicació::Telemàtica i xarxes d'ordinadors
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshComputer architecture
dc.subject.lcshComputer storage devices
dc.subject.lcshMultiprocessors
dc.subject.otherMemory bandwith
dc.subject.otherMultiprocessors
dc.subject.otherInterconnection networks
dc.subject.otherPerformance evaluation
dc.titleAn approximate analysis of synchronous multiple bus
dc.typeExternal research report
dc.subject.lemacArquitectura d'ordinadors
dc.subject.lemacOrdinadors -- Dispositius de memòria
dc.subject.lemacMultiprocessadors
dc.contributor.groupUniversitat Politècnica de Catalunya. MAPS - Management, Pricing and Services in Next Generation Networks
dc.rights.accessOpen Access
local.identifier.drac21604400
dc.description.versionPostprint (published version)
local.citation.authorGonzález, L.; Sanvicente, E.


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