An approximate analysis of synchronous multiple bus

Abstract

This paper presents an approximate analytic model for evaluating the performance of a loosely coupled multiprocessor architecture whose memory, organized in modules, is shared by all the processors. Each memory module (Mi) is associated with a particular processor (Pi), and it may be accessed by this processor (local access) or by any other processor (Pj,j<>i) through b multiple shared bussed (external access). The performance indexes used in this paper are the memory bandwith B and the delay to access a memory module. The system is evaluated for different values of p' (p'=<1), the probability of memory service requirement in each memory cycle; therefore, we allow internal processing. Also we consider two kinds of system operation, depending upon the number of cycles needed to access the requested memory when the request is for an external module. These results are obtained rather easily by solving a set of algebraic equations that approximately describe the system in steady state, and that yield performance values extremely close to the simulation results.