Circuit design of a dual-versioning L1 data cache for optimistic concurrency
Tipus de documentReport de recerca
Condicions d'accésAccés obert
Projecte de la Comissió EuropeaHIPEAC - High Performance and Embedded Architecture and Compilation (EC-FP7-217068)
This paper proposes a novel L1 data cache design with dual-versioning SRAM cells (dvSRAM) for chip multi-processors (CMP) that implement optimistic concurrency proposals. In this new cache architecture, each dvSRAM cell has two cells, a main cell and a secondary cell, which keep two versions of the same data. These values can be accessed, modified, moved back and forth between the main and secondary cells within the access time of the cache. We design and simulate a 32-KB dual-versioning L1 data cache with 45nm CMOS technology at 2GHz processor frequency and 1V supply voltage, which we describe in detail. We also introduce three well-known use cases that make use of optimistic concurrency execution and that can benefit from our proposed design. Moreover, we evaluate one of the use cases to show the impact of the dual-versioning cell in both performance and energy consumption. Our experiments show that large speedups can be achieved with acceptable overall energy dissipation.
CitacióSeyedi, A., Armejach, A., Cristal, A., Unsal, O., Hur, I., Valero, M. "Circuit design of a dual-versioning L1 data cache for optimistic concurrency". 2011.