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dc.contributor.authorVallejo, Enrique
dc.contributor.authorSanyal, Sutirtha
dc.contributor.authorHarris, Tim
dc.contributor.authorVallejo, Fernando
dc.contributor.authorBeivide Palacio, Ramon
dc.contributor.authorUnsal, Osman Sabri
dc.contributor.authorCristal Kestelman, Adrián
dc.contributor.authorValero Cortés, Mateo
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2017-11-13T09:26:29Z
dc.date.available2017-11-13T09:26:29Z
dc.date.issued2008
dc.identifier.citationVallejo, E., Sanyal, S., Harris, T., Vallejo, F., Beivide, R., Unsal, O., Cristal, A., Valero, M. Towards fair, scalable, locking. A: Workshop on Exploiting Parallelism with Transactional Memory and other Hardware Assisted Methods. "Proceedings of the 2008 Workshop on Exploiting Parallelism with Transactional Memory and other Hardware Assisted Methods". Boston, Massachussetts: 2008, p. 1-6.
dc.identifier.urihttp://hdl.handle.net/2117/110451
dc.description.abstractWithout care, Hardware Transactional Memory presents several performance pathologies that can degrade its performance. Among them, writers of commonly read variables can suffer from starvation. Though different solutions have been proposed for HTM systems, hybrid systems can still suffer from this performance problem, given that software transactions don’t interact with the mechanisms used by hardware to avoid starvation. In this paper we introduce a new per-directory-line hardware contention management mechanism that allows fairer access between both software and hardware threads without the need to abort any transaction. Our mechanism is based on “reserving” directory lines, implementing a limited fair queue for the requests on that line. We adapt the mechanism to the LogTM conflict detection mechanism and show that the resulting proposal is deadlock free. Finally, we sketch how the idea could be applied more generally to reader-writer locks.
dc.format.extent6 p.
dc.language.isoeng
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshMemory management (Computer science)
dc.subject.lcshParallel processing (Electronic computers)
dc.subject.otherHardware transactional memory
dc.subject.otherReader starvation
dc.subject.otherSynchronization
dc.titleTowards fair, scalable, locking
dc.typeConference report
dc.subject.lemacGestió de memòria (Informàtica)
dc.subject.lemacProcessament en paral·lel (Ordinadors)
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.rights.accessOpen Access
local.identifier.drac21602402
dc.description.versionPostprint (published version)
local.citation.authorVallejo, E.; Sanyal, S.; Harris, T.; Vallejo, F.; Beivide, R.; Unsal, O.; Cristal, A.; Valero, M.
local.citation.contributorWorkshop on Exploiting Parallelism with Transactional Memory and other Hardware Assisted Methods
local.citation.pubplaceBoston, Massachussetts
local.citation.publicationNameProceedings of the 2008 Workshop on Exploiting Parallelism with Transactional Memory and other Hardware Assisted Methods
local.citation.startingPage1
local.citation.endingPage6


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